| Commit message (Expand) | Author | Age | Files | Lines |
* | usrp2: dont need to start streaming for this hack | Josh Blum | 2010-10-15 | 1 | -1/+0 |
* | usrp2: temp fix to send dummy packets and flush so FPGA vita machine are in k... | Josh Blum | 2010-10-15 | 1 | -0/+26 |
* | Merge branch 'flow_ctrl_with_fpga' | Josh Blum | 2010-10-15 | 77 | -405/+11159 |
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| * | Merge branch 'flow_control' into flow_ctrl | Josh Blum | 2010-10-14 | 57 | -256/+10817 |
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| | * | now handles frames larger than the vita packet (i.e. with padding) | Matt Ettus | 2010-10-12 | 1 | -6/+16 |
| | * | don't clear out following packets on an eob ack | Matt Ettus | 2010-10-12 | 1 | -1/+1 |
| | * | don't flag an error on eob ack | Matt Ettus | 2010-10-12 | 1 | -1/+1 |
| | * | proper triggering for interrupts generated on the dsp_clk | Matt Ettus | 2010-10-12 | 1 | -1/+8 |
| | * | cleanup for 32 bit seqnum | Matt Ettus | 2010-10-11 | 1 | -4/+3 |
| | * | increase compatibility number for flow control | Matt Ettus | 2010-10-11 | 1 | -1/+1 |
| | * | switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate | Matt Ettus | 2010-10-11 | 3 | -14/+16 |
| | * | send message on eob to ack the end of transmission | Matt Ettus | 2010-10-11 | 1 | -1/+6 |
| | * | typo which isn't caught by xilinx | Matt Ettus | 2010-10-11 | 1 | -1/+1 |
| | * | separated flow control and error reporting on tx path. should work with and ... | Matt Ettus | 2010-10-10 | 4 | -25/+43 |
| | * | go to the correct state | Matt Ettus | 2010-10-08 | 1 | -3/+3 |
| | * | add a fifo to the end of the mux to help in timing. | Matt Ettus | 2010-10-08 | 1 | -6/+13 |
| | * | add trigger to makefile | Matt Ettus | 2010-10-08 | 1 | -0/+1 |
| | * | assign setting reg addresses | Matt Ettus | 2010-10-08 | 1 | -2/+2 |
| | * | declarations | Matt Ettus | 2010-10-08 | 1 | -2/+3 |
| | * | checkpoint in flow control packet generation | Matt Ettus | 2010-10-08 | 5 | -42/+147 |
| | * | revert unneeded changes and incorrect comments | Matt Ettus | 2010-10-07 | 3 | -38/+38 |
| | * | reconnect GPIOs, remove debug pins, meets timing now | Matt Ettus | 2010-10-06 | 1 | -5/+3 |
| | * | Merge branch 'ise12' into efifo_merge_dcm | Matt Ettus | 2010-10-06 | 3 | -29/+23 |
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| | | * | fix timing problem on DAC output bus | Matt Ettus | 2010-10-01 | 1 | -2/+2 |
| | * | | Modified phase shift of DCM1 to -64 which is intended to give more timing mar... | Ian Buckley | 2010-09-30 | 1 | -1/+1 |
| | * | | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S... | Ian Buckley | 2010-09-14 | 1 | -12/+12 |
| | * | | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i... | Ian Buckley | 2010-09-01 | 4 | -5/+101 |
| | * | | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ef... | Ian Buckley | 2010-09-01 | 5 | -47/+60 |
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| | | * | | hangedddddddextrnal fifo size to use full NoBL SRAM | ianb | 2010-08-25 | 1 | -1/+1 |
| | | * | | Corrected extfifo code so that all registers that are on SRAM signals are pac... | ianb | 2010-08-25 | 5 | -46/+59 |
| | * | | | Enhanced test bench to be more like real world application | Ian Buckley | 2010-09-01 | 2 | -7/+14 |
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| | * | | capacity logic fix | Matt Ettus | 2010-08-19 | 1 | -1/+1 |
| | * | | Added capacity to the module pinout | Ian Buckley | 2010-08-19 | 1 | -3/+4 |
| | * | | Added a bunch of debug signals. | Ian Buckley | 2010-08-19 | 4 | -9/+19 |
| | * | | Merge branch 'ise12_efifo_work' into efifo_merge | Matt Ettus | 2010-08-19 | 8 | -236/+113 |
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| | | * | | Regenerated FIFO with lower trigger level for almost full flag to reflect log... | Ian Buckley | 2010-08-19 | 9 | -238/+115 |
| | * | | | Merge branch 'features' into ise12_efifo_merge | Matt Ettus | 2010-08-16 | 2 | -3/+6 |
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| | * \ \ \ | Matt's attempt at merging | Matt Ettus | 2010-08-16 | 10 | -5569/+306 |
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| | * \ \ \ \ | Merge branch 'ise12' into ise12_efifo_work | Matt Ettus | 2010-08-16 | 10 | -33/+180 |
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| | * | | | | | Regenerated FIFO's for extfifo. | Ian Buckley | 2010-08-12 | 12 | -728/+19 |
| | * | | | | | Edited FIFO instance to delete port that was not regenerated after reconfigur... | Ian Buckley | 2010-08-12 | 1 | -1/+0 |
| | * | | | | | Adding in files that probably didn;t exist in the ISE10.1 version of coregen | Ian Buckley | 2010-08-12 | 5 | -0/+808 |
| | * | | | | | Bringing all coregen files checked in into sync | Ian Buckley | 2010-08-12 | 10 | -137/+60 |
| | * | | | | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv in... | Ian Buckley | 2010-08-12 | 18 | -41/+587 |
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| | | * | | | | | checkin of generated coregen files | Matt Ettus | 2010-08-11 | 18 | -8/+556 |
| | * | | | | | | Found bug due to not accounting for the correct number of possible in flight ... | Ian Buckley | 2010-08-12 | 7 | -49/+113 |
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| | * | | | | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-07-31 | 19 | -238/+7327 |
| | * | | | | | Checkpoint checkin. | Ian Buckley | 2010-07-29 | 13 | -0/+1507 |
| | * | | | | | get it to build | Matt Ettus | 2010-07-14 | 5 | -5/+309 |
| | * | | | | | moved forward from the old branch | Matt Ettus | 2010-07-14 | 8 | -4/+876 |