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* Merge branch 'flow_ctrl' into nextJosh Blum2010-11-2380-371/+11313
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| * Firmware mem map changes for flow ctrl somehow didn't get propagated.Nick Foster2010-11-183-2/+7
| * Updated fw rev number in N2XX burner.Nick Foster2010-11-181-2/+1
| * Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into flow_ctrlNick Foster2010-11-17120-690/+8268
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| * | usrp2: implemented clear state for RX and TX control, and zero sample command...Josh Blum2010-11-087-44/+10
| * | Merge branch 'master' into flow_ctrlJosh Blum2010-11-05156-4428/+1762
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| * \ \ Merge branch 'master' into flow_ctrlJosh Blum2010-10-2815-69/+376
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| * \ \ \ Merge branch 'next' into flow_ctrlJosh Blum2010-10-2738-345/+1237
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| * | | | | dbsrx: allow for setup time after changing the vco selectionJosh Blum2010-10-241-0/+3
| * | | | | BasicRX: GPIOs now output 0 to decrease noise pickup.Nick Foster2010-10-221-0/+5
| * | | | | Merge branch 'master' into flow_ctrlJosh Blum2010-10-221-0/+2
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| * | | | | | images: remove exe bit left by some build processesJosh Blum2010-10-221-0/+1
| * | | | | | Merge branch 'flow_control_fpga' into flow_ctrlJosh Blum2010-10-227-115/+304
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| | * | | | | | the width of the address bus is called DEPTH, not WIDTH...Matt Ettus2010-10-211-2/+2
| | * | | | | | address gray codingMatt Ettus2010-10-211-1/+7
| | * | | | | | slow slew rate and lower drive to 8ma on RAM_XX signals to reduce emiMatt Ettus2010-10-211-43/+43
| | * | | | | | should combine the randomizer with flow_controlMatt Ettus2010-10-215-71/+254
| * | | | | | | Merge branch 'garp' into flow_ctrlJosh Blum2010-10-226-102/+145
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| * \ \ \ \ \ \ \ Merge branch 'usrp2_overflow' into flow_ctrlJosh Blum2010-10-214-2/+19
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| * \ \ \ \ \ \ \ \ Merge branch 'master' into flow_ctrlJosh Blum2010-10-2133-718/+2166
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| * \ \ \ \ \ \ \ \ \ Merge branch 'master' into flow_ctrlJosh Blum2010-10-181-1/+1
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| * | | | | | | | | | | usrp2: dont need to start streaming for this hackJosh Blum2010-10-151-1/+0
| * | | | | | | | | | | usrp2: temp fix to send dummy packets and flush so FPGA vita machine are in k...Josh Blum2010-10-151-0/+26
| * | | | | | | | | | | Merge branch 'flow_ctrl_with_fpga'Josh Blum2010-10-1577-405/+11159
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| | * \ \ \ \ \ \ \ \ \ \ Merge branch 'flow_control' into flow_ctrlJosh Blum2010-10-1457-256/+10817
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| | | * | | | | | | | | | now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-10-121-6/+16
| | | * | | | | | | | | | don't clear out following packets on an eob ackMatt Ettus2010-10-121-1/+1
| | | * | | | | | | | | | don't flag an error on eob ackMatt Ettus2010-10-121-1/+1
| | | * | | | | | | | | | proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-10-121-1/+8
| | | * | | | | | | | | | cleanup for 32 bit seqnumMatt Ettus2010-10-111-4/+3
| | | * | | | | | | | | | increase compatibility number for flow controlMatt Ettus2010-10-111-1/+1
| | | * | | | | | | | | | switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-10-113-14/+16
| | | * | | | | | | | | | send message on eob to ack the end of transmissionMatt Ettus2010-10-111-1/+6
| | | * | | | | | | | | | typo which isn't caught by xilinxMatt Ettus2010-10-111-1/+1
| | | * | | | | | | | | | separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-10-104-25/+43
| | | * | | | | | | | | | go to the correct stateMatt Ettus2010-10-081-3/+3
| | | * | | | | | | | | | add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
| | | * | | | | | | | | | add trigger to makefileMatt Ettus2010-10-081-0/+1
| | | * | | | | | | | | | assign setting reg addressesMatt Ettus2010-10-081-2/+2
| | | * | | | | | | | | | declarationsMatt Ettus2010-10-081-2/+3
| | | * | | | | | | | | | checkpoint in flow control packet generationMatt Ettus2010-10-085-42/+147
| | | * | | | | | | | | | revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
| | | * | | | | | | | | | reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
| | | * | | | | | | | | | Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
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| | | | * | | | | | | | | | fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| | | * | | | | | | | | | | Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-09-301-1/+1
| | | * | | | | | | | | | | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-09-141-12/+12
| | | * | | | | | | | | | | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-09-014-5/+101
| | | * | | | | | | | | | | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ef...Ian Buckley2010-09-015-47/+60
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| | | | * | | | | | | | | | | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
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