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* Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| * Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
* | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
* | remove unused portMatt Ettus2009-09-101-1/+1
* | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
* | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
* | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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* Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
* parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
* remove unused old style fifoMatt Ettus2009-09-041-31/+0
* allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
* debug the rx sideMatt Ettus2009-09-041-1/+6
* no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
* seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
* MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus2009-09-034-67/+70
* set device to xc3s2000. Shouldn't make any differences.Matt Ettus2009-09-031-2/+2
* misc ignoresMatt Ettus2009-09-032-0/+3
* made a new block ram based fifo, 64 (65) elements long, all fifos now have "e...Matt Ettus2009-09-0328-155/+652
* bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
* major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
* cleaning up the new fifosMatt Ettus2009-09-023-155/+0
* cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an...Matt Ettus2009-09-024-56/+2
* never used, not neededMatt Ettus2009-09-024-441/+0
* debug pins, cleaned ignoresMatt Ettus2009-09-023-9/+22
* sort out active-low lines on locallink fifos, added debug pinsMatt Ettus2009-09-021-3/+15
* Removed these files completely, they were for the old style of fifosMatt Ettus2009-09-024-497/+0
* fixed addressing of registers, and added write enables to those that were mis...Matt Ettus2009-09-011-6/+9
* Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-3125-957/+693
* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-1321-0/+331
* Add custom FPGA build.jcorgan2009-07-3012-3/+1704
* Fix swapped signals.jcorgan2009-04-272-2/+3
* Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPG...jcorgan2009-04-228-0/+776
* mostly formatting and name changes. commented out special purpose pins.matt2009-04-121-180/+180
* from u2p2, autogeneratedmatt2009-04-121-279/+353
* now handles odd length packetsmatt2009-04-061-6/+9
* basic wrapper workingmatt2009-04-043-9/+240
* Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and strea...jcorgan2009-04-042-2/+23
* first cut at a wishbone interface and wrapping the corematt2009-04-044-6/+221
* copied over from other eth corematt2009-04-044-0/+928
* reset synchronizermatt2009-04-041-0/+16
* made pause enabling a pin so we can set itmatt2009-04-032-5/+4
* Properly signals an error and drops the remainder of the packet if there is a...matt2009-04-021-6/+12
* more thorough tests, including overrun, underrun, crc err, etc.matt2009-04-021-34/+42
* simulate a hiccup in the filling of the fifo. If long enough, will cause a t...matt2009-04-021-0/+15
* debug ports for fifo level testing. Normally I wouldn't check this in, but a...matt2009-04-021-3/+3
* Fix for fifo overruns on eth rx in full duplex. Now send re-pause long befor...matt2009-04-023-6/+14
* test multiple error typesmatt2009-04-021-6/+30
* added a state to ensure the error signal propagates, and now we assert src_rd...matt2009-04-021-9/+13
* only write one error into fifomatt2009-04-021-1/+1
* generate error signalmatt2009-04-021-3/+3