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* uhd: added tx dc offset calibration + tweaksJosh Blum2011-11-146-49/+325
* usrp: fixed default initialization of iq bal correctionJosh Blum2011-11-133-6/+6
* uhd: share more common code in cal utilsJosh Blum2011-11-113-94/+56
* Merge branch 'fpga_cal_work' into calibrationJosh Blum2011-11-116-8/+8
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| * need more umph out of correction valuesJosh Blum2011-11-106-8/+8
* | uhd: created rx IQ imbalance app to parallel txJosh Blum2011-11-118-93/+489
* | uhd: lots of tweaks for calibration utilityJosh Blum2011-11-112-43/+49
* | Updates to accommodate loopback calibration modeJason Abele2011-11-114-30/+71
* | usrp: basically working iq cal on txJosh Blum2011-11-1012-33/+396
* | uhd: basically usable cal sweep for wbxJosh Blum2011-11-104-70/+164
* | uhd: first stab at calibration appJosh Blum2011-11-092-0/+244
* | usrp: added missing include for weak ptrJosh Blum2011-11-082-0/+2
* | usrp1: fix typo when calculating rx_dc_offset registerJosh Blum2011-11-081-1/+1
* | Clip WBX target freq before computing LO settingsJason Abele2011-11-083-0/+9
* | uhd: useful tweaks from userJosh Blum2011-11-082-1/+2
* | Merge branch 'uhd_next'Josh Blum2011-11-07152-6665/+7312
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| * | Merge branch 'fpga_master' into uhd_nextJosh Blum2011-11-0727-372/+1342
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| | * remove unused irq to meet timingJosh Blum2011-11-052-21/+7
| | * convenience makefiles for top level projectsJosh Blum2011-11-052-0/+31
| | * increase vita rx fifosize to 10, like USRP2, make things workJosh Blum2011-11-042-4/+4
| | * dsp: remove dsp_buffer and replace with simpler add_routing_header,Matt Ettus2011-11-043-3/+50
| | * dsp: remove warningsMatt Ettus2011-11-042-4/+6
| | * u1e: fix unattached nets from copy-paste errorMatt Ettus2011-11-041-3/+3
| | * b100: fix warnings, complete removal of test codeMatt Ettus2011-11-042-16/+7
| | * b100: remove test features from GPIF to save spaceMatt Ettus2011-11-042-82/+9
| | * u1e/u1p: GPIOs switched over to setting regsMatt Ettus2011-10-272-32/+45
| | * forgot to add gpio atr to makefile source listJosh Blum2011-10-261-0/+1
| | * 32 bit compat number for E and B seriesJosh Blum2011-10-262-10/+8
| | * u1e/u1p: removed led setting regMatt Ettus2011-10-262-14/+4
| | * u1p/u1e: partially redone atr and gpio redoMatt Ettus2011-10-262-33/+11
| | * u2/u2p: use new setting_reg based gpios, gets it off of wbMatt Ettus2011-10-263-17/+98
| | * u1e/u1p: remove unused UARTMatt Ettus2011-10-262-24/+0
| | * u2/u2p: move nearly all setting regs onto dsp_clkMatt Ettus2011-10-262-30/+37
| | * u2/u2p: remove dead comments and codeMatt Ettus2011-10-262-84/+16
| | * dsp: make rounding a single bit work againMatt Ettus2011-10-261-5/+13
| | * dsp: new rounding. more complex, but better propertiesMatt Ettus2011-10-262-3/+80
| | * dsp_engine: don't use SD rounding in 8 bit mode, so we can have a flat noise ...Matt Ettus2011-10-262-4/+5
| | * dsp_engine: trailer change to fit standardMatt Ettus2011-10-261-2/+2
| | * dsp_engine fix rst -> reset, default to read addressMatt Ettus2011-10-262-3/+3
| | * dspengine: move the register to VITA_RX_CTRL + 9 instead of + 3 which is occu...Matt Ettus2011-10-261-1/+1
| | * dspengine: insert into the rx chainMatt Ettus2011-10-264-2/+29
| | * dsp_engine: new way of doing DSP operations on VITA packets. Example does 16...Matt Ettus2011-10-267-3/+899
| | * dsp: ability to set rx dc offset to a fixed valueMatt Ettus2011-10-261-1/+2
| | * usrp2: fix typo in top level core filesJosh Blum2011-10-262-2/+2
| * | uhd: removed wax and props utilsJosh Blum2011-11-0711-453/+3
| * | Updated typos in XCVR2450 dboard property tree codeJason Abele2011-11-071-6/+6
| * | uhd: dont pass 0 sample buffs to converter (avoid segfaults)Josh Blum2011-11-073-3/+6
| * | usrp2: fix channel mapping calculationJosh Blum2011-11-071-2/+2
| * | uhd: modify examples to use new time/clock source APIJosh Blum2011-11-076-69/+13
| * | uhd: bumped version number for next branch workJosh Blum2011-11-071-2/+2
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