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* Merge branch 'fpga_master'Josh Blum2012-03-114-101/+3
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| * fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
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* | usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
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* | Changes Windows installer filename to match naming convention of Ubuntu and ↵Nicholas Corgan2012-02-291-0/+1
| | | | | | | | Fedora installers
* | uhd: fix sc16 to sc8 conversion tableJosh Blum2012-02-291-12/+12
| | | | | | | | | | | | | | 1) this was registered as the sc8 to sc16 converter, probably messed that up as well 2) the cast to index was wrong, now unit test passes
* | usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
| | | | | | | | | | | | | | 1) use bottom bit for force lock condition, that way we never check the time after proper shutdown 2) dont allow lock condition under fpga compat mismatch
* | Changing UHD to 'USRP HD' in one last place.Ben Hilburn2012-02-281-1/+1
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* | usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
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* | Changes images CMakeLists.txt to be consistent with new UHD version naming ↵Nicholas Corgan2012-02-281-6/+5
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* | uhd: fixed some compile warnings for msvcJosh Blum2012-02-284-5/+5
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* | cmake:Nicholas Corgan2012-02-284-14/+17
| | | | | | | | | | | | | | More git info used for build info UHD version incorporates build info apt/yum repos use new version number New installer filename syntax
* | uhd: fixed send pkt handler, vrt packet type was uninitializedJosh Blum2012-02-271-0/+1
| | | | | | | | | | | | | | This fixes a bug where the sc8 engine will not interpret the packet as an IF data packet due to uninitialized bits. In that case the sc8 packet would pass through and be interpreted by the downstream as an sc16 packet.
* | usrp2: removed unused memory map entriesJosh Blum2012-02-271-5/+1
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* | usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
| | | | | | | | | | | | | | | | Unlike the other products, usrp1 uses the DAC and not DSP to perform baseband frequency shifting in the hardware. Therefore this shifting occurs before I and Q swapping, and so, the sign of the frequency needs to be inverted on daughterboards which have inverted I and Q TX inputs.
* | usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
| | | | | | | | | | Must subtract off the 511 for 512 modulus remainder commit. This bug was introduced by the conversion to streamer API.
* | Try really hard to get cmake to use compiler flags from the toolchain file.Philip Balister2012-02-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | See: http://www.mail-archive.com/cmake@cmake.org/msg33248.html Also credit to OpenEmbedded for doing something similar in the toolchain file they create. Note that adding the SYSTEM_NAME to the toolchain file sets CROSS_COMPILING, which is not what we want for native compiling. Signed-off-by: Philip Balister <philip@opensdr.com>
* | usb: added /opt/local to libusb search pathJosh Blum2012-02-211-1/+2
| | | | | | | | For OSX from MLD
* | usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
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* | usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
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* | usrp2: changed download url for dd.exeJosh Blum2012-02-182-2/+2
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* | Merge branch 'fpga_master'Josh Blum2012-02-183-4/+26
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| * usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| | | | | | | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero.
| * vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
| | | | | | | | | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes.
* | uhd: added -fvisibility-inlines-hiddenJosh Blum2012-02-181-1/+2
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* | Merge branch 'next'Josh Blum2012-02-17123-1729/+3954
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| * | Merge branch 'fpga_next' into nextJosh Blum2012-02-1754-1070/+2565
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| | * dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
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| | * dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
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| | * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
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| | * dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | | | | | | | | | | | all n-series devices meet timing
| | * dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | | | | | | | | | | | | | | | | | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested.
| | * dsp rework: pass enables into glue, update power trig, parameterize, fix ↵Josh Blum2012-02-109-103/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build
| | * dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
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| | * B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
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| | * dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
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| | * b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
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| | * b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
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| | * power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
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| | * dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0226-262/+544
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| | * power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
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| | * dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
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| | * dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
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| | * dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
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| | * Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
| | |\ | | | | | | | | | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v
| | | * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
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| | | * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
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| | | * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
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| | | * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
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| | | * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
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| | * | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
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