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* make the testbench work in this environment, without the crossclock settings busMatt Ettus2009-12-083-5/+8
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* be a little more PC about itMatt Ettus2009-11-181-5/+9
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* mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
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* forgot to declare wiresMatt Ettus2009-11-061-0/+4
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* moved regs around for vita49Matt Ettus2009-11-052-12/+13
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* vita rx instead of rx_control. Ready for firmware testing. Misses timing ↵Matt Ettus2009-11-054-4/+48
| | | | by a little bit, will worry later.
* put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-053-8/+17
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* VITA49 rx (and tx skeleton) copied over from quad radioMatt Ettus2009-11-057-0/+1026
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* This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-044-15/+259
| | | | | | The counter is for performance monitoring in firmware, priority encoder and new interrupt controller are from quad radio and speed up interrupts. This is tested and it works for me.
* earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
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* Properly reset the fifos. We didn't connect before.Matt Ettus2009-10-051-5/+5
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* Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan2009-10-01613-90023/+2518
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'new_eth' of http://gnuradio.org/git/matt: (42 commits) Fix warnings, mostly from implicitly defined wires or unspecified widths fullchip sim now compiles again, after moving eth and models over to new simple_gemac remove unused opencores remove debugging code no idea where this came from, it shouldn't be here Copied wb_1master back from quad radio Remove old mac. Good riddance. remove unused port More xilinx fifos, more clean up of our fifos might as well use a cascade fifo to help timing and give a little more capacity fix a typo which caused tx glitches Untested fixes for getting serdes onto the new fifo system. Compiles, at least Implement Eth flow control using pause frames parameterized fifo sizes, some reformatting remove unused old style fifo allow control of whether or not to honor flow control, adds some debug lines debug the rx side no longer used, replaced by newfifo version remove special last_line adjustment from ethernet port Firmware now inserts mac source address value in each frame. ...
| * Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-016-8/+14
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| * fullchip sim now compiles again, after moving eth and models over to new ↵Matt Ettus2009-10-015-17/+159
| | | | | | | | simple_gemac
| * remove unused opencoresMatt Ettus2009-10-01463-71885/+0
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| * Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-302-224/+239
| |\ | | | | | | | | | | | | | | | | | | Functionality should not change at all Conflicts: usrp2/fpga/top/u2_core/u2_core.v
| | * Copied wb_1master back from quad radioMatt Ettus2009-09-302-223/+238
| | | | | | | | | | | | more sane config options, should be exactly the same memory map
| * | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
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| * | Merge commit 'origin' into new_ethMatt Ettus2009-09-243-11/+24
| |\| | | | | | | | | | | | | Conflicts: .gitignore
| * | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| | * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
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| * | | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
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| * | | remove unused portMatt Ettus2009-09-101-1/+1
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| * | | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
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| * | | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
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| * | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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| * | Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
| | | | | | | | | | | | | | | | | | Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though.
| * | parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
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| * | remove unused old style fifoMatt Ettus2009-09-041-31/+0
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| * | allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
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| * | debug the rx sideMatt Ettus2009-09-041-1/+6
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| * | no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
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| * | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
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| * | MAC transmit seems to work now. The root cause of the problem was ↵Matt Ettus2009-09-034-67/+70
| | | | | | | | | | | | accidentally using the rx_clk in one stage of the fifos on the tx side.
| * | set device to xc3s2000. Shouldn't make any differences.Matt Ettus2009-09-031-2/+2
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| * | misc ignoresMatt Ettus2009-09-032-0/+3
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| * | made a new block ram based fifo, 64 (65) elements long, all fifos now have ↵Matt Ettus2009-09-0328-155/+652
| | | | | | | | | | | | "enhanced level logic" for accurate fullness. Maybe this will help...
| * | bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
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| * | major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
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| * | cleaning up the new fifosMatt Ettus2009-09-023-155/+0
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| * | cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v ↵Matt Ettus2009-09-024-56/+2
| | | | | | | | | | | | and fifo_2clock.v are empty
| * | never used, not neededMatt Ettus2009-09-024-441/+0
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| * | debug pins, cleaned ignoresMatt Ettus2009-09-023-9/+22
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| * | sort out active-low lines on locallink fifos, added debug pinsMatt Ettus2009-09-021-3/+15
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| * | Removed these files completely, they were for the old style of fifosMatt Ettus2009-09-024-497/+0
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| * | fixed addressing of registers, and added write enables to those that were ↵Matt Ettus2009-09-011-6/+9
| | | | | | | | | | | | missing. MDIO seems ok.
| * | Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-3125-957/+693
| | | | | | | | | | | | | | | | | | | | | * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz.
* | | Enable pps interrupts. Not sure why they were disabled in the first place.Matt Ettus2009-09-291-3/+2
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* | Synchronize the internal phase of the halfband filters to the start of the ↵Matt Ettus2009-09-243-11/+24
|/ | | | "run" signal. This is important for MIMO. Bug reported by Christoph Hein and Hanwen .
* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-1321-0/+331
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