diff options
Diffstat (limited to 'vrt/vita_tx_tb.v')
| -rw-r--r-- | vrt/vita_tx_tb.v | 99 |
1 files changed, 71 insertions, 28 deletions
diff --git a/vrt/vita_tx_tb.v b/vrt/vita_tx_tb.v index 94b7bdd0b..62532c07c 100644 --- a/vrt/vita_tx_tb.v +++ b/vrt/vita_tx_tb.v @@ -2,9 +2,11 @@ module vita_tx_tb; - localparam INTERP = 8'd4; + localparam DECIM = 8'd4; + localparam INTERP = 8'd4; + localparam MAXCHAN=4; - localparam NUMCHAN=4; + localparam NUMCHAN=1; reg clk = 0; reg reset = 1; @@ -12,14 +14,15 @@ module vita_tx_tb; initial #1000 reset = 0; always #50 clk = ~clk; - initial $dumpfile("vita_rx_tb.vcd"); - initial $dumpvars(0,vita_rx_tb); + initial $dumpfile("vita_tx_tb.vcd"); + initial $dumpvars(0,vita_tx_tb); wire [(MAXCHAN*32)-1:0] sample; wire strobe, run; wire [35:0] data_o; wire src_rdy; - reg dst_rdy = 1; + wire dst_rdy; + wire [63:0] vita_time; reg set_stb = 0; @@ -29,41 +32,63 @@ module vita_tx_tb; wire [7:0] set_addr_dsp; wire [31:0] set_data_dsp; + /* settings_bus_crossclock settings_bus_xclk_dsp (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - + */ + wire sample_dst_rdy, sample_src_rdy; //wire [99:0] sample_data_o; - wire [64+4+(MAXCHAN*32)-1:0] sample_data_o; + wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; + + time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit + (.clk(clk), .rst(reset), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(0), .vita_time(vita_time)); + + rx_dsp_model rx_dsp_model + (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0])); + generate + if(MAXCHAN>1) + assign sample[(MAXCHAN*32)-1:32] = 0; + endgenerate + vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .vita_time(vita_time), .overrun(overrun), .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), .sample(sample), .run(run), .strobe(strobe)); vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy), .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), .fifo_occupied(), .fifo_full(), .fifo_empty() ); - - rx_dsp_model rx_dsp_model - (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0])); - generate - if(MAXCHAN>1) - assign sample[(MAXCHAN*32)-1:32] = 0; - endgenerate + wire [35:0] data_tx; + wire src_rdy_tx, dst_rdy_tx; + wire sample_dst_rdy_tx, sample_src_rdy_tx; - time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit - (.clk(clk), .rst(reset), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(0), .vita_time(vita_time)); + fifo_long #(.WIDTH(36)) fifo_short + (.clk(clk), .reset(reset), .clear(0), + .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx)); + vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN)) vita_tx_deframer + (.clk(clk), .reset(reset), .clear(0), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx), + .sample_fifo_o(sample_data_tx), + .sample_fifo_dst_rdy_i(sample_dst_rdy_tx), .sample_fifo_src_rdy_o(sample_src_rdy_tx), + .fifo_occupied(), .fifo_full(), .fifo_empty() ); + + tx_dsp_model tx_dsp_model + (.clk(clk), .reset(reset), .run(run), .interp(INTERP), .strobe(strobe), .sample(sample[31:0] )); + always @(posedge clk) if(src_rdy & dst_rdy) begin @@ -90,13 +115,14 @@ module vita_tx_tb; begin @(negedge reset); @(posedge clk); - write_setting(4,32'hDEADBEEF); // VITA header + write_setting(4,32'h14900008); // VITA header write_setting(5,32'hF00D1234); // VITA streamid write_setting(6,32'h98765432); // VITA trailer write_setting(7,8); // Samples per VITA packet write_setting(8,NUMCHAN); // Samples per VITA packet queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet - queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth +/* + queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet @@ -124,19 +150,19 @@ module vita_tx_tb; queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd length #100000; - dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun + //dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent #100000; - dst_rdy <= 1; // restart the reads so we can see what we got + //dst_rdy <= 1; // restart the reads so we can see what we got #100000; - dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun + //dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent #100000; @(posedge clk); - dst_rdy <= 1; - + //dst_rdy <= 1; + */ #100000 $finish; end @@ -167,7 +193,8 @@ module vita_tx_tb; end endtask // queue_rx_cmd -endmodule // rx_control_tb +endmodule // vita_tx_tb + module rx_dsp_model (input clk, input reset, @@ -209,3 +236,19 @@ module rx_dsp_model assign strobe = stb_ctr == decim-1; endmodule // rx_dsp_model + +module tx_dsp_model + (input clk, input reset, + input run, + input [7:0] interp, + output strobe, + input [31:0] sample); + + cic_strober strober(.clock(clk), .reset(reset), .enable(run), .rate(interp), .strobe_fast(1), .strobe_slow(strobe)); + + always @(posedge clk) + if(strobe) + $display("Time %d, Sent Sample %x",$time,sample); + + +endmodule // tx_dsp_model |