diff options
Diffstat (limited to 'usrp2')
25 files changed, 494 insertions, 259 deletions
diff --git a/usrp2/custom/Makefile.srcs b/usrp2/custom/Makefile.srcs deleted file mode 100644 index 8a4f70fca..000000000 --- a/usrp2/custom/Makefile.srcs +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2012 Ettus Research LLC -# - -################################################## -# FIFO Sources -################################################## -CUSTOM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../custom/, \ -custom_dsp_rx.v \ -custom_dsp_tx.v \ -custom_engine_rx.v \ -custom_engine_tx.v \ -)) diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v index 73294566e..b90cd54e9 100644 --- a/usrp2/custom/custom_dsp_rx.v +++ b/usrp2/custom/custom_dsp_rx.v @@ -15,7 +15,7 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // -//CUSTOMIZE ME! +//COPY ME, CUSTOMIZE ME... //The following module effects the IO of the DDC chain. //By default, this entire module is a simple pass-through. @@ -31,9 +31,6 @@ module custom_dsp_rx #( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - //frontend bus width parameter WIDTH = 24 ) @@ -41,11 +38,8 @@ module custom_dsp_rx //control signals input clock, input reset, input enable, - //main settings bus for built-in modules - input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, - //user settings bus, controlled through user setting regs API - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + input set_stb, input [7:0] set_addr, input [31:0] set_data, //full rate inputs directly from the RX frontend input [WIDTH-1:0] frontend_i, @@ -61,49 +55,12 @@ module custom_dsp_rx //strobbed baseband samples {I16,Q16} from this module output [31:0] bb_sample, - output bb_strobe, //high on valid sample - - //debug output (optional) - output [31:0] debug + output bb_strobe //high on valid sample ); - generate - if (DSPNO==0) begin - `ifndef RX_DSP0_MODULE - assign ddc_in_i = frontend_i; - assign ddc_in_q = frontend_q; - assign bb_sample = ddc_out_sample; - assign bb_strobe = ddc_out_strobe; - `else - RX_DSP0_CUSTOM_MODULE_NAME rx_dsp0_custom - ( - .clock(clock), .reset(reset), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q), - .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - else begin - `ifndef RX_DSP1_MODULE - assign ddc_in_i = frontend_i; - assign ddc_in_q = frontend_q; - assign bb_sample = ddc_out_sample; - assign bb_strobe = ddc_out_strobe; - `else - RX_DSP1_CUSTOM_MODULE_NAME rx_dsp1_custom - ( - .clock(clock), .reset(reset), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q), - .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - endgenerate + assign ddc_in_i = frontend_i; + assign ddc_in_q = frontend_q; + assign bb_sample = ddc_out_sample; + assign bb_strobe = ddc_out_strobe; endmodule //custom_dsp_rx diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v index cb0d7522b..4b1388b02 100644 --- a/usrp2/custom/custom_dsp_tx.v +++ b/usrp2/custom/custom_dsp_tx.v @@ -15,7 +15,7 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // -//CUSTOMIZE ME! +//COPY ME, CUSTOMIZE ME... //The following module effects the IO of the DUC chain. //By default, this entire module is a simple pass-through. @@ -31,9 +31,6 @@ module custom_dsp_tx #( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - //frontend bus width parameter WIDTH = 24 ) @@ -41,11 +38,8 @@ module custom_dsp_tx //control signals input clock, input reset, input enable, - //main settings bus for built-in modules - input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, - //user settings bus, controlled through user setting regs API - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + input set_stb, input [7:0] set_addr, input [31:0] set_data, //full rate outputs directly to the TX frontend output [WIDTH-1:0] frontend_i, @@ -61,49 +55,12 @@ module custom_dsp_tx //strobbed baseband samples {I16,Q16} to this module input [31:0] bb_sample, - output bb_strobe, //this is a backpressure signal - - //debug output (optional) - output [31:0] debug + output bb_strobe //this is a backpressure signal ); - generate - if (DSPNO==0) begin - `ifndef TX_DSP0_MODULE - assign frontend_i = duc_out_i; - assign frontend_q = duc_out_q; - assign duc_in_sample = bb_sample; - assign bb_strobe = duc_in_strobe; - `else - TX_DSP0_CUSTOM_MODULE_NAME tx_dsp0_custom - ( - .clock(clock), .reset(reset), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), - .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - else begin - `ifndef TX_DSP1_MODULE - assign frontend_i = duc_out_i; - assign frontend_q = duc_out_q; - assign duc_in_sample = bb_sample; - assign bb_strobe = duc_in_strobe; - `else - TX_DSP1_CUSTOM_MODULE_NAME tx_dsp1_custom - ( - .clock(clock), .reset(reset), .enable(enable), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .frontend_i(frontend_i), .frontend_q(frontend_q), - .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), - .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), - .bb_sample(bb_sample), .bb_strobe(bb_strobe) - ); - `endif - end - endgenerate + assign frontend_i = duc_out_i; + assign frontend_q = duc_out_q; + assign duc_in_sample = bb_sample; + assign bb_strobe = duc_in_strobe; endmodule //custom_dsp_tx diff --git a/usrp2/custom/custom_engine_rx.v b/usrp2/custom/custom_engine_rx.v index 48276665f..dfeaad2cd 100644 --- a/usrp2/custom/custom_engine_rx.v +++ b/usrp2/custom/custom_engine_rx.v @@ -15,35 +15,26 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // -//CUSTOMIZE ME! +//COPY ME, CUSTOMIZE ME... //The following module is used to re-write receive packets to the host. //This module provides a packet-based ram interface for manipulating packets. //The user writes a custom engine (state machine) to read the input packet, -//and to produce a new output packet. For users customizing the DSP operation, -//your customizations may be better suited for the custom_dsp_rx module. -//By default, this module uses the built-in 16 to 8 bit converter engine. +//and to produce a new output packet. + +//By default, this entire module is a simple pass-through. module custom_engine_rx #( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - //buffer size for ram interface engine - parameter BUF_SIZE = 10, - - //base address for built-in settings registers used in this module - parameter MAIN_SETTINGS_BASE = 0 + parameter BUF_SIZE = 10 ) ( //control signals input clock, input reset, input clear, - //main settings bus for built-in modules - input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, - //user settings bus, controlled through user setting regs API - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + input set_stb, input [7:0] set_addr, input [31:0] set_data, //ram interface for engine output access_we, @@ -54,47 +45,9 @@ module custom_engine_rx output [BUF_SIZE-1:0] access_adr, input [BUF_SIZE-1:0] access_len, output [35:0] access_dat_o, - input [35:0] access_dat_i, - - //debug output (optional) - output [31:0] debug + input [35:0] access_dat_i ); - generate - if (DSPNO==0) begin - `ifndef RX_ENG0_MODULE - dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - else begin - `ifndef RX_ENG1_MODULE - dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - endgenerate + assign access_done = access_ok; endmodule //custom_engine_rx diff --git a/usrp2/custom/custom_engine_tx.v b/usrp2/custom/custom_engine_tx.v index 6227b0f45..9be728484 100644 --- a/usrp2/custom/custom_engine_tx.v +++ b/usrp2/custom/custom_engine_tx.v @@ -15,26 +15,20 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // -//CUSTOMIZE ME! +//COPY ME, CUSTOMIZE ME... //The following module is used to re-write transmit packets from the host. //This module provides a packet-based ram interface for manipulating packets. //The user writes a custom engine (state machine) to read the input packet, -//and to produce a new output packet. For users customizing the DSP operation, -//your customizations may be better suited for the custom_dsp_tx module. -//By default, this module uses the built-in 8 to 16 bit converter engine. +//and to produce a new output packet. + +//By default, this entire module is a simple pass-through. module custom_engine_tx #( - //the dsp unit number: 0, 1, 2... - parameter DSPNO = 0, - //buffer size for ram interface engine parameter BUF_SIZE = 10, - //base address for built-in settings registers used in this module - parameter MAIN_SETTINGS_BASE = 0, - //the number of 32bit lines between start of buffer and vita header //the metadata before the header should be preserved by the engine parameter HEADER_OFFSET = 0 @@ -43,11 +37,8 @@ module custom_engine_tx //control signals input clock, input reset, input clear, - //main settings bus for built-in modules - input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, - //user settings bus, controlled through user setting regs API - input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + input set_stb, input [7:0] set_addr, input [31:0] set_data, //ram interface for engine output access_we, @@ -58,47 +49,9 @@ module custom_engine_tx output [BUF_SIZE-1:0] access_adr, input [BUF_SIZE-1:0] access_len, output [35:0] access_dat_o, - input [35:0] access_dat_i, - - //debug output (optional) - output [31:0] debug + input [35:0] access_dat_i ); - generate - if (DSPNO==0) begin - `ifndef TX_ENG0_MODULE - dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) tx_eng0_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - else begin - `ifndef TX_ENG1_MODULE - dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16 - (.clk(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `else - TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) tx_eng1_custom - (.clock(clock),.reset(reset),.clear(clear), - .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), - .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), - .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), - .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); - `endif - end - endgenerate + assign access_done = access_ok; endmodule //custom_engine_tx diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs index 840627e6d..e6c4c5343 100644 --- a/usrp2/sdr_lib/Makefile.srcs +++ b/usrp2/sdr_lib/Makefile.srcs @@ -40,4 +40,6 @@ sign_extend.v \ small_hb_dec.v \ small_hb_int.v \ tx_frontend.v \ +dsp_tx_glue.v \ +dsp_rx_glue.v \ )) diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v index 270da45db..3dee978a5 100644 --- a/usrp2/sdr_lib/ddc_chain.v +++ b/usrp2/sdr_lib/ddc_chain.v @@ -165,10 +165,9 @@ module ddc_chain round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out()); - custom_dsp_rx #(.DSPNO(DSPNO)) custom( + dsp_rx_glue #(.DSPNO(DSPNO)) custom( .clock(clk), .reset(rst), .enable(run), - .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux), .ddc_in_i(to_cordic_i), .ddc_in_q(to_cordic_q), .ddc_out_sample(ddc_chain_out), .ddc_out_strobe(ddc_chain_stb), diff --git a/usrp2/sdr_lib/dsp_rx_glue.v b/usrp2/sdr_lib/dsp_rx_glue.v new file mode 100644 index 000000000..2c7c188e0 --- /dev/null +++ b/usrp2/sdr_lib/dsp_rx_glue.v @@ -0,0 +1,95 @@ +// +// Copyright 2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +//The following module effects the IO of the DDC chain. +//By default, this entire module is a simple pass-through. + +module dsp_rx_glue +#( + //the dsp unit number: 0, 1, 2... + parameter DSPNO = 0, + + //frontend bus width + parameter WIDTH = 24 +) +( + //control signals + input clock, input reset, input enable, + + //user settings bus, controlled through user setting regs API + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + //full rate inputs directly from the RX frontend + input [WIDTH-1:0] frontend_i, + input [WIDTH-1:0] frontend_q, + + //full rate outputs directly to the DDC chain + output [WIDTH-1:0] ddc_in_i, + output [WIDTH-1:0] ddc_in_q, + + //strobed samples {I16,Q16} from the RX DDC chain + input [31:0] ddc_out_sample, + input ddc_out_strobe, //high on valid sample + + //strobbed baseband samples {I16,Q16} from this module + output [31:0] bb_sample, + output bb_strobe, //high on valid sample + + //debug output (optional) + output [31:0] debug +); + + generate + if (DSPNO==0) begin + `ifndef RX_DSP0_MODULE + assign ddc_in_i = frontend_i; + assign ddc_in_q = frontend_q; + assign bb_sample = ddc_out_sample; + assign bb_strobe = ddc_out_strobe; + `else + RX_DSP0_MODULE rx_dsp0_custom + ( + .clock(clock), .reset(reset), .enable(enable), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .frontend_i(frontend_i), .frontend_q(frontend_q), + .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q), + .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), + .bb_sample(bb_sample), .bb_strobe(bb_strobe) + ); + `endif + end + else begin + `ifndef RX_DSP1_MODULE + assign ddc_in_i = frontend_i; + assign ddc_in_q = frontend_q; + assign bb_sample = ddc_out_sample; + assign bb_strobe = ddc_out_strobe; + `else + RX_DSP1_MODULE rx_dsp1_custom + ( + .clock(clock), .reset(reset), .enable(enable), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .frontend_i(frontend_i), .frontend_q(frontend_q), + .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q), + .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), + .bb_sample(bb_sample), .bb_strobe(bb_strobe) + ); + `endif + end + endgenerate + +endmodule //dsp_rx_glue diff --git a/usrp2/sdr_lib/dsp_tx_glue.v b/usrp2/sdr_lib/dsp_tx_glue.v new file mode 100644 index 000000000..8eccd2bfc --- /dev/null +++ b/usrp2/sdr_lib/dsp_tx_glue.v @@ -0,0 +1,95 @@ +// +// Copyright 2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +//The following module effects the IO of the DUC chain. +//By default, this entire module is a simple pass-through. + +module dsp_tx_glue +#( + //the dsp unit number: 0, 1, 2... + parameter DSPNO = 0, + + //frontend bus width + parameter WIDTH = 24 +) +( + //control signals + input clock, input reset, input enable, + + //user settings bus, controlled through user setting regs API + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + //full rate outputs directly to the TX frontend + output [WIDTH-1:0] frontend_i, + output [WIDTH-1:0] frontend_q, + + //full rate outputs directly from the DUC chain + input [WIDTH-1:0] duc_out_i, + input [WIDTH-1:0] duc_out_q, + + //strobed samples {I16,Q16} to the TX DUC chain + output [31:0] duc_in_sample, + input duc_in_strobe, //this is a backpressure signal + + //strobbed baseband samples {I16,Q16} to this module + input [31:0] bb_sample, + output bb_strobe, //this is a backpressure signal + + //debug output (optional) + output [31:0] debug +); + + generate + if (DSPNO==0) begin + `ifndef TX_DSP0_MODULE + assign frontend_i = duc_out_i; + assign frontend_q = duc_out_q; + assign duc_in_sample = bb_sample; + assign bb_strobe = duc_in_strobe; + `else + TX_DSP0_MODULE tx_dsp0_custom + ( + .clock(clock), .reset(reset), .enable(enable), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .frontend_i(frontend_i), .frontend_q(frontend_q), + .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), + .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), + .bb_sample(bb_sample), .bb_strobe(bb_strobe) + ); + `endif + end + else begin + `ifndef TX_DSP1_MODULE + assign frontend_i = duc_out_i; + assign frontend_q = duc_out_q; + assign duc_in_sample = bb_sample; + assign bb_strobe = duc_in_strobe; + `else + TX_DSP1_MODULE tx_dsp1_custom + ( + .clock(clock), .reset(reset), .enable(enable), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .frontend_i(frontend_i), .frontend_q(frontend_q), + .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), + .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe), + .bb_sample(bb_sample), .bb_strobe(bb_strobe) + ); + `endif + end + endgenerate + +endmodule //dsp_tx_glue diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v index d9ede6bc2..d3b2b394f 100644 --- a/usrp2/sdr_lib/duc_chain.v +++ b/usrp2/sdr_lib/duc_chain.v @@ -147,10 +147,9 @@ module duc_chain .R(rst) // Synchronous reset input ); - custom_dsp_tx #(.DSPNO(DSPNO)) custom( + dsp_tx_glue #(.DSPNO(DSPNO)) dsp_tx_glue( .clock(clk), .reset(rst), .enable(run), - .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), - .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .frontend_i(tx_fe_i), .frontend_q(tx_fe_q), .duc_out_i(prod_i[33:10]), .duc_out_q(prod_q[33:10]), .duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1), diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100 index 442b0b579..3cdbb62c0 100644 --- a/usrp2/top/B100/Makefile.B100 +++ b/usrp2/top/B100/Makefile.B100 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -7,7 +7,14 @@ ################################################## TOP_MODULE := B100 BUILD_DIR := build-B100/ -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## include ../Makefile.common include ../../fifo/Makefile.srcs @@ -21,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../gpif/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## # Project Properties @@ -64,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_MOD_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 4c3acaa27..88a8b4f4b 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -37,7 +37,7 @@ module u1plus_core input pps_in ); - localparam TXFIFOSIZE = 12; + localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 12; // 64 total regs in address space @@ -220,7 +220,7 @@ module u1plus_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(0/*no engine*/), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100 index 397bac618..ad5a0c1bd 100644 --- a/usrp2/top/E1x0/Makefile.E100 +++ b/usrp2/top/E1x0/Makefile.E100 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u1e BUILD_DIR = $(abspath build$(ISE)-E100) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../gpmc/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## # Project Properties @@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_MOD_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110 index 1f95954ae..291ac0a44 100644 --- a/usrp2/top/E1x0/Makefile.E110 +++ b/usrp2/top/E1x0/Makefile.E110 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u1e BUILD_DIR = $(abspath build$(ISE)-E110) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../gpmc/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## # Project Properties @@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_MOD_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 5f2edca1a..765023e29 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -220,7 +220,7 @@ module u1e_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3 index 7181e7d62..680cadf44 100644 --- a/usrp2/top/N2x0/Makefile.N200R3 +++ b/usrp2/top/N2x0/Makefile.N200R3 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2plus BUILD_DIR = $(abspath build$(ISE)-N200R3) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4 index 551f7a232..5c9ffd7a6 100644 --- a/usrp2/top/N2x0/Makefile.N200R4 +++ b/usrp2/top/N2x0/Makefile.N200R4 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2plus BUILD_DIR = $(abspath build$(ISE)-N200R4) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -69,7 +72,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1" +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index 2514600f4..0b53ac951 100644 --- a/usrp2/top/N2x0/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2plus BUILD_DIR = $(abspath build$(ISE)-N210R3) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 951df0c7c..a7d2a9b49 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2plus BUILD_DIR = $(abspath build$(ISE)-N210R4) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -69,7 +72,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1" +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile index adfaf06c4..1fc375c76 100644 --- a/usrp2/top/USRP2/Makefile +++ b/usrp2/top/USRP2/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2_rev3 BUILD_DIR = $(abspath build) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index 166ed44ef..84ba5dc29 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -15,4 +15,6 @@ vita_tx_chain.v \ gen_context_pkt.v \ trigger_context_pkt.v \ vita_pkt_gen.v \ +vita_rx_engine_glue.v \ +vita_tx_engine_glue.v \ )) diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index bd416f563..e4f7e9864 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -74,7 +74,7 @@ module vita_rx_chain .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); - custom_engine_rx #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_rx + vita_rx_engine_glue #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+3), .BUF_SIZE(FIFOSIZE)) dspengine_rx (.clock(clk),.reset(reset),.clear(clear), .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), diff --git a/usrp2/vrt/vita_rx_engine_glue.v b/usrp2/vrt/vita_rx_engine_glue.v new file mode 100644 index 000000000..86e3d1114 --- /dev/null +++ b/usrp2/vrt/vita_rx_engine_glue.v @@ -0,0 +1,95 @@ +// +// Copyright 2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +//The following module is used to re-write receive packets to the host. +//This module provides a packet-based ram interface for manipulating packets. +//By default, this module uses the built-in 16 to 8 bit converter engine. + +module vita_rx_engine_glue +#( + //the dsp unit number: 0, 1, 2... + parameter DSPNO = 0, + + //buffer size for ram interface engine + parameter BUF_SIZE = 10, + + //base address for built-in settings registers used in this module + parameter MAIN_SETTINGS_BASE = 0 +) +( + //control signals + input clock, input reset, input clear, + + //main settings bus for built-in modules + input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, + + //user settings bus, controlled through user setting regs API + input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + + //ram interface for engine + output access_we, + output access_stb, + input access_ok, + output access_done, + output access_skip_read, + output [BUF_SIZE-1:0] access_adr, + input [BUF_SIZE-1:0] access_len, + output [35:0] access_dat_o, + input [35:0] access_dat_i, + + //debug output (optional) + output [31:0] debug +); + + generate + if (DSPNO==0) begin + `ifndef RX_ENG0_MODULE + dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8 + (.clk(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `else + RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom + (.clock(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `endif + end + else begin + `ifndef RX_ENG1_MODULE + dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8 + (.clk(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `else + RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom + (.clock(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `endif + end + endgenerate + +endmodule //vita_rx_engine_glue diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 78f63b555..93bc703cd 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -19,6 +19,7 @@ module vita_tx_chain #(parameter BASE=0, parameter FIFOSIZE=10, + parameter POST_ENGINE_FIFOSIZE=10, parameter REPORT_ERROR=0, parameter DO_FLOW_CONTROL=0, parameter PROT_ENG_FLAGS=0, @@ -75,6 +76,8 @@ module vita_tx_chain wire [FIFOSIZE-1:0] access_adr, access_len; wire access_we, access_stb, access_ok, access_done, access_skip_read; wire [35:0] dsp_to_buf, buf_to_dsp; + wire [35:0] tx_data_int0; + wire tx_src_rdy_int0, tx_dst_rdy_int0; double_buffer #(.BUF_SIZE(FIFOSIZE)) db (.clk(clk),.reset(reset),.clear(clear), @@ -83,15 +86,21 @@ module vita_tx_chain .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), - .data_o(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1)); + .data_o(tx_data_int0), .src_rdy_o(tx_src_rdy_int0), .dst_rdy_i(tx_dst_rdy_int0)); - custom_engine_tx #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+6), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_tx + vita_tx_engine_glue #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+1), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_tx (.clock(clk),.reset(reset),.clear(clear), .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); + + fifo_cascade #(.WIDTH(36), .SIZE(POST_ENGINE_FIFOSIZE)) post_engine_buffering( + .clk(clk), .reset(reset), .clear(clear), + .datain(tx_data_int0), .src_rdy_i(tx_src_rdy_int0), .dst_rdy_o(tx_dst_rdy_int0), + .dataout(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1)); + end endgenerate diff --git a/usrp2/vrt/vita_tx_engine_glue.v b/usrp2/vrt/vita_tx_engine_glue.v new file mode 100644 index 000000000..b0a81c3e9 --- /dev/null +++ b/usrp2/vrt/vita_tx_engine_glue.v @@ -0,0 +1,99 @@ +// +// Copyright 2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +//The following module is used to re-write transmit packets from the host. +//This module provides a packet-based ram interface for manipulating packets. +//By default, this module uses the built-in 8 to 16 bit converter engine. + +module vita_tx_engine_glue +#( + //the dsp unit number: 0, 1, 2... + parameter DSPNO = 0, + + //buffer size for ram interface engine + parameter BUF_SIZE = 10, + + //base address for built-in settings registers used in this module + parameter MAIN_SETTINGS_BASE = 0, + + //the number of 32bit lines between start of buffer and vita header + //the metadata before the header should be preserved by the engine + parameter HEADER_OFFSET = 0 +) +( + //control signals + input clock, input reset, input clear, + + //main settings bus for built-in modules + input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main, + + //user settings bus, controlled through user setting regs API + input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + + //ram interface for engine + output access_we, + output access_stb, + input access_ok, + output access_done, + output access_skip_read, + output [BUF_SIZE-1:0] access_adr, + input [BUF_SIZE-1:0] access_len, + output [35:0] access_dat_o, + input [35:0] access_dat_i, + + //debug output (optional) + output [31:0] debug +); + + generate + if (DSPNO==0) begin + `ifndef TX_ENG0_MODULE + dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16 + (.clk(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `else + TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom + (.clock(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `endif + end + else begin + `ifndef TX_ENG1_MODULE + dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16 + (.clk(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `else + TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom + (.clock(clock),.reset(reset),.clear(clear), + .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); + `endif + end + endgenerate + +endmodule //vita_tx_engine_glue |