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-rw-r--r--usrp2/control_lib/settings_fifo_ctrl.v12
-rw-r--r--usrp2/top/N2x0/u2plus_core.v16
-rw-r--r--usrp2/top/USRP2/u2_core.v16
-rw-r--r--usrp2/vrt/vita_rx_framer.v8
-rw-r--r--usrp2/vrt/vita_tx_deframer.v3
5 files changed, 30 insertions, 25 deletions
diff --git a/usrp2/control_lib/settings_fifo_ctrl.v b/usrp2/control_lib/settings_fifo_ctrl.v
index 160112169..3aa6b7ec7 100644
--- a/usrp2/control_lib/settings_fifo_ctrl.v
+++ b/usrp2/control_lib/settings_fifo_ctrl.v
@@ -238,20 +238,22 @@ module settings_fifo_ctrl
reg [31:0] command_hdr_reg;
reg [31:0] command_data_reg;
- wire now, early, late, too_early;
+ reg [63:0] vita_time_reg;
+ always @(posedge clock)
+ vita_time_reg <= vita_time;
+
+ wire late;
`ifndef FIFO_CTRL_NO_TIME
time_compare time_compare(
- .time_now(vita_time), .trigger_time(command_ticks_reg),
- .now(now), .early(early), .late(late), .too_early(too_early));
+ .time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
`else
- assign now = 0;
assign late = 1;
`endif
//action occurs in the event state and when there is fifo space (should always be true)
//the third condition is that all peripherals in the perfs signal are ready/active high
//the fourth condition is that is an event time has been set, action is delayed until that time
- wire time_ready = (out_command_has_time)? (now || late) : 1;
+ wire time_ready = (out_command_has_time)? late : 1;
wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
assign command_fifo_read = action;
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 703e157cc..e2539e183 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -456,11 +456,11 @@ module u2plus_core
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
- .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
- .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(status),.word09(32'hffff_ffff),.word10(32'hffff_ffff),
.word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
- .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
+ .word14(32'hffff_ffff),.word15(32'hffff_ffff)
);
// /////////////////////////////////////////////////////////////////////////
@@ -522,10 +522,10 @@ module u2plus_core
.in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready),
.out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready),
.strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
- .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
- .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
.debug(sfc_debug)
);
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 9038ab788..cd277762a 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -464,11 +464,11 @@ module u2_core
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
- .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
- .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(status),.word09(32'hffff_ffff),.word10(32'hffff_ffff),
.word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
- .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
+ .word14(32'hffff_ffff),.word15(32'hffff_ffff)
);
// /////////////////////////////////////////////////////////////////////////
@@ -530,10 +530,10 @@ module u2_core
.in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready),
.out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready),
.strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
- .word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
- .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
.debug(sfc_debug)
);
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index 514df1151..6e4b8025d 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -85,9 +85,11 @@ module vita_rx_framer
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(samples_per_packet),.changed());
- setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan
+ assign numchan = 0;/*
+ setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(0)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
+ */
// Output FIFO for packetized data
localparam VITA_IDLE = 0;
@@ -164,7 +166,7 @@ module vita_rx_framer
VITA_PAYLOAD :
if(sample_fifo_src_rdy_i)
begin
- if(sample_phase == (numchan-4'd1))
+ if(sample_phase == numchan)
begin
sample_phase <= 0;
sample_ctr <= sample_ctr + 1;
@@ -213,7 +215,7 @@ module vita_rx_framer
assign data_o[35:34] = 2'b00; // Always write full lines
assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
( ((vita_state==VITA_PAYLOAD) &
- (sample_phase == (numchan-4'd1)) &
+ (sample_phase == numchan) &
~|flags_fifo_o[4:1]) |
(vita_state==VITA_ERR_PAYLOAD));
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 6919da11a..ed3916311 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -43,10 +43,11 @@ module vita_tx_deframer
localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
- wire [1:0] numchan;
+ wire [1:0] numchan = 0;/*
setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
+ */
reg [3:0] vita_state;
wire has_streamid, has_classid, has_secs, has_tics, has_trailer;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-20 17:45:37 +0000