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-rw-r--r--usrp2/extramfifo/ext_fifo.v10
-rw-r--r--usrp2/extramfifo/nobl_fifo.v4
-rw-r--r--usrp2/extramfifo/nobl_if.v12
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v17
-rw-r--r--usrp2/top/u2_rev3/u2_rev3.ucf64
5 files changed, 60 insertions, 47 deletions
diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index b17fde10b..2af59a75d 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -38,7 +38,8 @@ module ext_fifo
output [INT_WIDTH-1:0] dataout,
output src_rdy_o, // not EMPTY
input dst_rdy_i, // READ
- output reg [31:0] debug
+ output reg [31:0] debug,
+ output reg [31:0] debug2
);
wire [EXT_WIDTH-1:0] write_data;
@@ -111,9 +112,12 @@ module ext_fifo
assign src_rdy_o = ~empty2;
always @ (posedge int_clk)
- debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i };
+ debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
always @ (posedge ext_clk)
- debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] };
+ debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
+ always@ (posedge ext_clk)
+// debug2[31:0] <= {write_data[15:0],read_data[15:0]};
+ debug2[31:0] <= 0;
endmodule // ext_fifo
diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v
index 62229e6c2..4c009d980 100644
--- a/usrp2/extramfifo/nobl_fifo.v
+++ b/usrp2/extramfifo/nobl_fifo.v
@@ -47,7 +47,7 @@ module nobl_fifo
capacity <= (1 << FIFO_DEPTH) - 1;
wr_pointer <= 0;
rd_pointer <= 0;
- space_avail <= 0;
+ space_avail <= 1;
data_avail_int <= 0;
end
else
@@ -56,7 +56,7 @@ module nobl_fifo
// Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision)
space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );
// Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO.
- data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && read) );
+ data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) );
wr_pointer <= wr_pointer + write;
rd_pointer <= rd_pointer + (~write && read);
capacity <= capacity - write + (~write && read) ;
diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v
index 24d463b1e..391a841e8 100644
--- a/usrp2/extramfifo/nobl_if.v
+++ b/usrp2/extramfifo/nobl_if.v
@@ -9,11 +9,11 @@ module nobl_if
output [WIDTH-1:0] RAM_D_po,
output reg RAM_D_poe,
output [DEPTH-1:0] RAM_A,
- output RAM_WEn,
+ output reg RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
- output RAM_CE1n,
+ output reg RAM_CE1n,
input [DEPTH-1:0] address,
input [WIDTH-1:0] data_out,
output reg [WIDTH-1:0] data_in,
@@ -54,11 +54,15 @@ module nobl_if
else
begin
enable_pipe1 <= enable;
+ RAM_CE1n <= ~enable; // Creates IOB flob
+
if (enable)
begin
address_pipe1 <= address;
write_pipe1 <= write;
+ RAM_WEn <= ~write; // Creates IOB flob
+
if (write)
data_out_pipe1 <= data_out;
@@ -68,8 +72,8 @@ module nobl_if
// Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
assign RAM_A = address_pipe1;
assign RAM_CENn = 1'b0;
- assign RAM_WEn = ~write_pipe1;
- assign RAM_CE1n = ~enable_pipe1;
+ // assign RAM_WEn = ~write_pipe1;
+// assign RAM_CE1n = ~enable_pipe1;
//
// Pipeline stage2
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index ced67072e..2682926f6 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -171,7 +171,7 @@ module u2_core
wire [31:0] atr_lines;
wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
- debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo;
+ debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2;
wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
@@ -414,7 +414,7 @@ module u2_core
.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
.dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
- .gpio( {io_tx,io_rx} ) );
+ .gpio(/* {io_tx,io_rx}*/ ) );
// /////////////////////////////////////////////////////////////////////////
// Buffer Pool Status -- Slave #5
@@ -665,7 +665,7 @@ module u2_core
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
-----/\----- EXCLUDED -----/\----- */
- ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(8))
+ ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19))
ext_fifo_i1
(
.int_clk(dsp_clk),
@@ -681,13 +681,16 @@ module u2_core
.RAM_LDn(RAM_LDn),
.RAM_OEn(RAM_OEn),
.RAM_CE1n(RAM_CE1n),
- .datain({rd1_flags,rd1_dat}),
+// .datain({rd1_flags,rd1_dat}),
+ .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
.src_rdy_i(rd1_ready_o), // WRITE
.dst_rdy_o(rd1_ready_i), // not FULL
- .dataout(tx_data),
+// .dataout(tx_data),
+ .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
.src_rdy_o(tx_src_rdy), // not EMPTY
.dst_rdy_i(tx_dst_rdy),
- .debug(debug_extfifo)
+ .debug(debug_extfifo),
+ .debug2(debug_extfifo2)
);
vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
@@ -789,6 +792,8 @@ module u2_core
assign debug = debug_extfifo;
assign debug_gpio_0 = 32'd0;
assign debug_gpio_1 = 32'd0;
+ assign {io_tx,io_rx} = debug_extfifo2;
+
endmodule // u2_core
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 82d879446..bf9569fe4 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ;
NET "sen_tx_dac" LOC = "H4" ;
NET "sclk_tx_dac" LOC = "J5" ;
NET "sdi_tx_dac" LOC = "J6" ;
-NET "io_tx[0]" LOC = "K4" ;
-NET "io_tx[1]" LOC = "K3" ;
-NET "io_tx[2]" LOC = "G1" ;
-NET "io_tx[3]" LOC = "G5" ;
-NET "io_tx[4]" LOC = "H5" ;
-NET "io_tx[5]" LOC = "F3" ;
-NET "io_tx[6]" LOC = "F2" ;
-NET "io_tx[7]" LOC = "F5" ;
-NET "io_tx[8]" LOC = "G6" ;
-NET "io_tx[9]" LOC = "E2" ;
-NET "io_tx[10]" LOC = "E1" ;
-NET "io_tx[11]" LOC = "E3" ;
-NET "io_tx[12]" LOC = "F4" ;
-NET "io_tx[13]" LOC = "D2" ;
-NET "io_tx[14]" LOC = "D4" ;
-NET "io_tx[15]" LOC = "E4" ;
+NET "io_tx[0]" LOC = "K4" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[1]" LOC = "K3" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[2]" LOC = "G1" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[3]" LOC = "G5" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[4]" LOC = "H5" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[5]" LOC = "F3" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[6]" LOC = "F2" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[7]" LOC = "F5" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[8]" LOC = "G6" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[9]" LOC = "E2" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[10]" LOC = "E1" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[11]" LOC = "E3" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[12]" LOC = "F4" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[13]" LOC = "D2" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[14]" LOC = "D4" |DRIVE = 12 |SLEW = FAST ;
+NET "io_tx[15]" LOC = "E4" |DRIVE = 12 |SLEW = FAST ;
NET "sen_rx_db" LOC = "D22" ;
NET "sclk_rx_db" LOC = "F19" ;
NET "sdo_rx_db" LOC = "G20" ;
@@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ;
NET "sen_rx_dac" LOC = "J18" ;
NET "sclk_rx_dac" LOC = "J19" ;
NET "sdi_rx_dac" LOC = "J21" ;
-NET "io_rx[0]" LOC = "L21" ;
-NET "io_rx[1]" LOC = "L20" ;
-NET "io_rx[2]" LOC = "L19" ;
-NET "io_rx[3]" LOC = "L18" ;
-NET "io_rx[4]" LOC = "L17" ;
-NET "io_rx[5]" LOC = "K22" ;
-NET "io_rx[6]" LOC = "K21" ;
-NET "io_rx[7]" LOC = "K20" ;
-NET "io_rx[8]" LOC = "G22" ;
-NET "io_rx[9]" LOC = "G21" ;
-NET "io_rx[10]" LOC = "F21" ;
-NET "io_rx[11]" LOC = "F20" ;
-NET "io_rx[12]" LOC = "G19" ;
-NET "io_rx[13]" LOC = "G18" ;
-NET "io_rx[14]" LOC = "G17" ;
-NET "io_rx[15]" LOC = "E22" ;
+NET "io_rx[0]" LOC = "L21" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[1]" LOC = "L20" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[2]" LOC = "L19" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[3]" LOC = "L18" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[4]" LOC = "L17" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[5]" LOC = "K22" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[6]" LOC = "K21" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[7]" LOC = "K20" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[8]" LOC = "G22" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[9]" LOC = "G21" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[10]" LOC = "F21" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[11]" LOC = "F20" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[12]" LOC = "G19" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[13]" LOC = "G18" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[14]" LOC = "G17" |DRIVE = 12 |SLEW = FAST ;
+NET "io_rx[15]" LOC = "E22" |DRIVE = 12 |SLEW = FAST ;
NET "clk_to_mac" TNM_NET = "clk_to_mac";
TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-19 13:25:40 +0000