diff options
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/opencores/zpu/core/zpu_config.vhd | 5 | ||||
| -rw-r--r-- | usrp2/opencores/zpu/core/zpu_core.vhd | 3 | ||||
| -rw-r--r-- | usrp2/opencores/zpu/core/zpupkg.vhd | 1 | ||||
| -rw-r--r-- | usrp2/opencores/zpu/wishbone/zpu_system.vhd | 3 | ||||
| -rw-r--r-- | usrp2/opencores/zpu/zpu_top_pkg.vhd | 2 | ||||
| -rw-r--r-- | usrp2/opencores/zpu/zpu_wb_top.vhd | 2 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 4 | ||||
| -rw-r--r-- | usrp2/top/u2plus/u2plus_core.v | 4 |
8 files changed, 12 insertions, 12 deletions
diff --git a/usrp2/opencores/zpu/core/zpu_config.vhd b/usrp2/opencores/zpu/core/zpu_config.vhd index b7e894232..f7743d602 100644 --- a/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/usrp2/opencores/zpu/core/zpu_config.vhd @@ -12,4 +12,9 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 15;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8";
+
end zpu_config;
diff --git a/usrp2/opencores/zpu/core/zpu_core.vhd b/usrp2/opencores/zpu/core/zpu_core.vhd index 24586b2f6..2450f14d3 100644 --- a/usrp2/opencores/zpu/core/zpu_core.vhd +++ b/usrp2/opencores/zpu/core/zpu_core.vhd @@ -26,7 +26,6 @@ entity zpu_core is mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); @@ -203,7 +202,7 @@ begin if areset = '1' then state <= State_Idle; break <= '0'; - sp <= stack_start(maxAddrBitIncIO downto minAddrBit); + sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; diff --git a/usrp2/opencores/zpu/core/zpupkg.vhd b/usrp2/opencores/zpu/core/zpupkg.vhd index eee967a09..1a01563b8 100644 --- a/usrp2/opencores/zpu/core/zpupkg.vhd +++ b/usrp2/opencores/zpu/core/zpupkg.vhd @@ -73,7 +73,6 @@ package zpupkg is mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
- stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
interrupt : in std_logic;
break : out std_logic;
zpu_status : out std_logic_vector(63 downto 0));
diff --git a/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/usrp2/opencores/zpu/wishbone/zpu_system.vhd index 8af678b6a..294651fe2 100644 --- a/usrp2/opencores/zpu/wishbone/zpu_system.vhd +++ b/usrp2/opencores/zpu/wishbone/zpu_system.vhd @@ -51,7 +51,7 @@ entity zpu_system is -- ZPU Control signals
enable : in std_logic;
interrupt : in std_logic;
- stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
+
zpu_status : out std_logic_vector(63 downto 0);
-- wishbone interfaces
@@ -84,7 +84,6 @@ begin mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
- stack_start => stack_start,
interrupt => interrupt,
zpu_status => zpu_status,
break => open);
diff --git a/usrp2/opencores/zpu/zpu_top_pkg.vhd b/usrp2/opencores/zpu/zpu_top_pkg.vhd index a158ab9c0..23ff48c39 100644 --- a/usrp2/opencores/zpu/zpu_top_pkg.vhd +++ b/usrp2/opencores/zpu/zpu_top_pkg.vhd @@ -35,7 +35,7 @@ package zpu_top_pkg is -- ZPU Control signals enable : in std_logic; interrupt : in std_logic; - stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); + zpu_status : out std_logic_vector(63 downto 0); -- wishbone interfaces diff --git a/usrp2/opencores/zpu/zpu_wb_top.vhd b/usrp2/opencores/zpu/zpu_wb_top.vhd index 9735c4b54..48e5ee31d 100644 --- a/usrp2/opencores/zpu/zpu_wb_top.vhd +++ b/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -36,7 +36,6 @@ entity zpu_wb_top is -- misc zpu signals interrupt: in std_logic; - stack_start: in std_logic_vector(adr_w-1 downto 0); zpu_status: out std_logic_vector(63 downto 0) ); @@ -67,7 +66,6 @@ zpu_system0: zpu_system port map( areset => rst, enable => enb, interrupt => interrupt, - stack_start => stack_start, zpu_status => zpu_status, zpu_wb_i => zpu_wb_i, zpu_wb_o => zpu_wb_o diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 63c711c1f..0e6120ec6 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -323,7 +323,7 @@ module u2_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone @@ -416,7 +416,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd5; + localparam compat_num = 32'd6; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index d3d80cc79..22e181caf 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -313,7 +313,7 @@ module u2plus_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone @@ -411,7 +411,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd5; + localparam compat_num = 32'd6; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), |