diff options
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/gpif/slave_fifo.v | 8 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 2 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 2 | ||||
| -rwxr-xr-x | usrp2/top/extract_usage.py | 60 | ||||
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 2 |
5 files changed, 67 insertions, 7 deletions
diff --git a/usrp2/gpif/slave_fifo.v b/usrp2/gpif/slave_fifo.v index b1d642fca..e75f28913 100644 --- a/usrp2/gpif/slave_fifo.v +++ b/usrp2/gpif/slave_fifo.v @@ -150,7 +150,7 @@ module slave_fifo STATE_DATA_RX: begin - if(data_rx_src_rdy && data_rx_dst_rdy && (transfer_count != data_transfer_size)) + if(data_rx_src_rdy && data_rx_dst_rdy) transfer_count <= transfer_count + 1; else state <= STATE_IDLE; @@ -170,7 +170,7 @@ module slave_fifo STATE_DATA_TX: begin - if(data_tx_dst_rdy && data_tx_src_rdy && (transfer_count != data_transfer_size)) + if(data_tx_dst_rdy && data_tx_src_rdy) transfer_count <= transfer_count + 1; else state <= STATE_IDLE; @@ -197,8 +197,8 @@ module slave_fifo // fifo signal assignments and enables //enable fifos - assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF; - assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE; + assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF && (transfer_count != data_transfer_size); + assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE && (transfer_count != data_transfer_size); assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX) && ~FX2_CF; assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX) && ~FX2_CE; diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 26714b669..c1d6767d1 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -413,7 +413,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd1}; //major, minor + localparam compat_num = {16'd9, 16'd3}; //major, minor wire [31:0] reg_test32; diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index ee27af939..a98e1de34 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -454,7 +454,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor + localparam compat_num = {16'd9, 16'd1}; //major, minor wire [31:0] reg_test32; diff --git a/usrp2/top/extract_usage.py b/usrp2/top/extract_usage.py new file mode 100755 index 000000000..55fbf384c --- /dev/null +++ b/usrp2/top/extract_usage.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python +# +# Copyright 2012 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +import os +import sys + +ALL_MAP_FILES = """\ +./N2x0/build-N210R4/u2plus_map.map N210 +./N2x0/build-N200R4/u2plus_map.map N200 +./USRP2/build/u2_rev3_map.map USRP2 +./E1x0/build-E100/u1e_map.map E100 +./E1x0/build-E110/u1e_map.map E110 +./B100/build-B100/B100_map.map B100 +""" + +def extract_map_from_file(path): + output = '' + found = False + for line in open(path).readlines(): + if line.strip() == 'Mapping completed.': found = False + if line.strip() == 'Logic Utilization:': found = True + if found: output += line + return output + +def extract_maps(): + output = '' + for line in ALL_MAP_FILES.splitlines(): + path, name = line.split() + if not os.path.exists(path): + print 'DNE ', path, ' skipping...' + output += """ + + + +######################################################################## +## %s Usage Summary +######################################################################## + +%s"""%(name, extract_map_from_file(path).strip()) + return output + '\n\n' + +if __name__ == '__main__': + summary = extract_maps() + if len(sys.argv) == 1: print summary + else: open(sys.argv[1], 'w').write(summary) diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index ca2f847bc..2788dc9d5 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -41,7 +41,7 @@ module vita_rx_chain wire clear; assign clear_o = clear; wire clear_int; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+8)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_int)); |