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-rw-r--r--usrp2/control_lib/double_buffer.v4
-rw-r--r--usrp2/vrt/vita_rx_chain.v2
2 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/control_lib/double_buffer.v b/usrp2/control_lib/double_buffer.v
index e8e565963..8865bddee 100644
--- a/usrp2/control_lib/double_buffer.v
+++ b/usrp2/control_lib/double_buffer.v
@@ -51,8 +51,8 @@ module double_buffer
reg [BUF_SIZE-1:0] len0, len1;
assign data_o = read_ptr ? data_o_1 : data_o_0;
- assign rw0_adr = (read_ok & ~read_ptr) ? read_adr : write_adr;
- assign rw1_adr = (read_ok & read_ptr) ? read_adr : write_adr;
+ assign rw0_adr = (write_ok & ~write_ptr) ? write_adr : read_adr;
+ assign rw1_adr = (write_ok & write_ptr) ? write_adr : read_adr;
wire [35:0] access_dat_o_0, access_dat_o_1;
wire access_ptr;
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index 14c454f8a..63e1e45dd 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -66,7 +66,7 @@ module vita_rx_chain
.data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2));
dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8
- (.clk(clk),.reset(rst),.clear(clear),
+ (.clk(clk),.reset(reset),.clear(clear),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),