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-rw-r--r--usrp2/control_lib/gpio_atr.v71
-rw-r--r--usrp2/top/N2x0/u2plus_core.v21
-rw-r--r--usrp2/top/USRP2/u2_core.v23
3 files changed, 98 insertions, 17 deletions
diff --git a/usrp2/control_lib/gpio_atr.v b/usrp2/control_lib/gpio_atr.v
new file mode 100644
index 000000000..82d72b815
--- /dev/null
+++ b/usrp2/control_lib/gpio_atr.v
@@ -0,0 +1,71 @@
+
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module gpio_atr
+ #(parameter BASE = 0,
+ parameter WIDTH = 32)
+ (input clk, input reset,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ input rx, input tx,
+ inout [WIDTH-1:0] gpio,
+ output reg [31:0] gpio_readback
+ );
+
+ wire [WIDTH-1:0] ddr, in_idle, in_tx, in_rx, in_fdx;
+ reg [WIDTH-1:0] rgpio, igpio;
+
+ setting_reg #(.my_addr(BASE+0), .width(WIDTH)) reg_idle
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+ .out(in_idle),.changed());
+
+ setting_reg #(.my_addr(BASE+1), .width(WIDTH)) reg_rx
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+ .out(in_rx),.changed());
+
+ setting_reg #(.my_addr(BASE+2), .width(WIDTH)) reg_tx
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+ .out(in_tx),.changed());
+
+ setting_reg #(.my_addr(BASE+3), .width(WIDTH)) reg_fdx
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+ .out(in_fdx),.changed());
+
+ setting_reg #(.my_addr(BASE+4), .width(WIDTH)) reg_ddr
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
+ .out(ddr),.changed());
+
+ always @(posedge clk)
+ case({tx,rx})
+ 2'b00: rgpio <= in_idle;
+ 2'b01: rgpio <= in_rx;
+ 2'b10: rgpio <= in_tx;
+ 2'b11: rgpio <= in_fdx;
+ endcase // case ({tx,rx})
+
+ integer n;
+ always @*
+ for(n=0;n<WIDTH;n=n+1)
+ igpio[n] <= ddr[n] ? rgpio[n] : 1'bz;
+
+ assign gpio = igpio;
+
+ always @(posedge clk)
+ gpio_readback <= gpio;
+
+endmodule // gpio_atr
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 2c547a245..861b3833f 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -163,6 +163,7 @@ module u2plus_core
localparam SR_TX_CTRL = 144; // 6
localparam SR_TX_DSP = 160; // 5
+ localparam SR_GPIO = 184; // 5
localparam SR_UDP_SM = 192; // 64
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
@@ -227,7 +228,7 @@ module u2plus_core
.s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K)
.s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI
.s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C
- .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO
+ .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // Unused
.s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback
.s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC
.s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K)
@@ -277,6 +278,7 @@ module u2plus_core
.sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
// Unused Slaves 9, b, c
+ assign s4_ack = 0;
assign s9_ack = 0; assign sb_ack = 0; assign sc_ack = 0;
// ////////////////////////////////////////////////////////////////////////////////////////
@@ -419,18 +421,21 @@ module u2plus_core
assign s3_dat_i[31:8] = 24'd0;
// /////////////////////////////////////////////////////////////////////////
- // GPIOs -- Slave #4
+ // GPIOs
- nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
- .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[4:0]),.we_i(s4_we),
- .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
- .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx), .gpio({io_tx,io_rx}) );
+ wire [31:0] gpio_readback;
+
+ gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
+ gpio_atr(.clk(dsp_clk),.reset(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx),
+ .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
// /////////////////////////////////////////////////////////////////////////
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd7, 16'd3}; //major, minor
+ localparam compat_num = {16'd8, 16'd0}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -438,7 +443,7 @@ module u2plus_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(32'b0),.word10(vita_time[63:32]),
+ .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 18bc50ac3..b4e17aa67 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -168,6 +168,7 @@ module u2_core
localparam SR_TX_CTRL = 144; // 6
localparam SR_TX_DSP = 160; // 5
+ localparam SR_GPIO = 184; // 5
localparam SR_UDP_SM = 192; // 64
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
@@ -233,7 +234,7 @@ module u2_core
.s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K)
.s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI
.s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C
- .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO
+ .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // Unused
.s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback
.s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC
.s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K)
@@ -282,7 +283,8 @@ module u2_core
.sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
.sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
- // Unused Slaves 9 and b-f
+ // Unused Slaves 4, 9 and b-f
+ assign s4_ack = 0;
assign s9_ack = 0; assign sb_ack = 0; assign sc_ack = 0;
assign sd_ack = 0; assign se_ack = 0; assign fc_ack = 0;
@@ -425,18 +427,21 @@ module u2_core
assign s3_dat_i[31:8] = 24'd0;
// /////////////////////////////////////////////////////////////////////////
- // GPIOs -- Slave #4
+ // GPIOs
- nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
- .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[4:0]),.we_i(s4_we),
- .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
- .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx), .gpio({io_tx,io_rx}) );
+ wire [31:0] gpio_readback;
+
+ gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
+ gpio_atr(.clk(dsp_clk),.reset(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx),
+ .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
// /////////////////////////////////////////////////////////////////////////
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd7, 16'd3}; //major, minor
+ localparam compat_num = {16'd8, 16'd0}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -444,7 +449,7 @@ module u2_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(32'b0),.word10(vita_time[63:32]),
+ .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 11:45:51 +0000