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-rw-r--r--usrp2/top/u1e/u1e_core.v10
1 files changed, 4 insertions, 6 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 903121832..4637df0cc 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,8 +1,8 @@
-//`define LOOPBACK 1
+`define LOOPBACK 1
//`define TIMED 1
-`define CRC 1
+//`define CRC 1
module u1e_core
(input clk_fpga, input rst_fpga,
@@ -372,12 +372,10 @@ module u1e_core
// Debug circuitry
assign debug_clk = { EM_CLK, clk_fpga };
-/*
- assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
{ EM_D } };
-*/
- assign debug = { phase[23:8], txsync, txblank, tx };
+ //assign debug = { phase[23:8], txsync, txblank, tx };
assign debug_gpio_0 = { debug_gpmc };