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-rw-r--r--usrp2/control_lib/user_settings.v2
-rw-r--r--usrp2/custom/Makefile.srcs11
-rw-r--r--usrp2/custom/custom_dsp_rx.v139
-rw-r--r--usrp2/custom/custom_dsp_tx.v139
-rw-r--r--usrp2/sdr_lib/ddc_chain.v23
-rw-r--r--usrp2/sdr_lib/duc_chain.v26
-rw-r--r--usrp2/top/B100/Makefile.B1003
-rw-r--r--usrp2/top/B100/u1plus_core.v11
-rw-r--r--usrp2/top/E1x0/Makefile.E1003
-rw-r--r--usrp2/top/E1x0/Makefile.E1103
-rw-r--r--usrp2/top/E1x0/u1e_core.v10
-rw-r--r--usrp2/top/N2x0/Makefile.N200R34
-rw-r--r--usrp2/top/N2x0/Makefile.N200R44
-rw-r--r--usrp2/top/N2x0/Makefile.N210R34
-rw-r--r--usrp2/top/N2x0/Makefile.N210R44
-rw-r--r--usrp2/top/N2x0/u2plus_core.v9
-rw-r--r--usrp2/top/USRP2/Makefile4
-rw-r--r--usrp2/top/USRP2/u2_core.v9
18 files changed, 370 insertions, 38 deletions
diff --git a/usrp2/control_lib/user_settings.v b/usrp2/control_lib/user_settings.v
index 96ee22427..d87f1de21 100644
--- a/usrp2/control_lib/user_settings.v
+++ b/usrp2/control_lib/user_settings.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Corgan Enterprises LLC
+// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
diff --git a/usrp2/custom/Makefile.srcs b/usrp2/custom/Makefile.srcs
new file mode 100644
index 000000000..22cf063c9
--- /dev/null
+++ b/usrp2/custom/Makefile.srcs
@@ -0,0 +1,11 @@
+#
+# Copyright 2012 Ettus Research LLC
+#
+
+##################################################
+# FIFO Sources
+##################################################
+CUSTOM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../custom/, \
+custom_dsp_rx.v \
+custom_dsp_tx.v \
+))
diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v
new file mode 100644
index 000000000..64f966c31
--- /dev/null
+++ b/usrp2/custom/custom_dsp_rx.v
@@ -0,0 +1,139 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+//CUSTOMIZE ME!
+
+//The following module effects the IO of the DDC chain.
+//By default, this entire module is a simple pass-through.
+
+//To implement DSP logic before the DDC:
+//Implement custom DSP between frontend and ddc input.
+
+//To implement DSP logic after the DDC:
+//Implement custom DSP between ddc output and baseband.
+
+//To bypass the DDC with custom logic:
+//Implement custom DSP between frontend and baseband.
+
+module custom_dsp_rx
+#(
+ parameter DSPNO = 0,
+ parameter ADCW = 24
+)
+(
+ //control signals
+ input clock, input reset, input enable,
+
+ //settings bus
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ //full rate inputs directly from the RX frontend
+ input [ADCW-1:0] frontend_i,
+ input [ADCW-1:0] frontend_q,
+
+ //full rate outputs directly to the DDC chain
+ output [ADCW-1:0] ddc_in_i,
+ output [ADCW-1:0] ddc_in_q,
+
+ //strobed samples {I16,Q16} from the RX DDC chain
+ input [31:0] ddc_out_sample,
+ input ddc_out_strobe, //high on valid sample
+
+ //strobbed baseband samples {I16,Q16} from this module
+ output [31:0] bb_sample,
+ output bb_strobe, //high on valid sample
+
+ //debug output (optional)
+ output [31:0] debug
+);
+
+ generate
+ if (DSPNO==0) begin
+ `ifndef RX_DSP0_MODULE
+ assign ddc_in_i = frontend_i;
+ assign ddc_in_q = frontend_q;
+ assign bb_sample = ddc_out_sample;
+ assign bb_strobe = ddc_out_strobe;
+ `else
+ RX_DSP0_CUSTOM_MODULE_NAME rx_dsp0_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
+ .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ if (DSPNO==1) begin
+ `ifndef RX_DSP1_MODULE
+ assign ddc_in_i = frontend_i;
+ assign ddc_in_q = frontend_q;
+ assign bb_sample = ddc_out_sample;
+ assign bb_strobe = ddc_out_strobe;
+ `else
+ RX_DSP1_CUSTOM_MODULE_NAME rx_dsp1_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
+ .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ if (DSPNO==2) begin
+ `ifndef RX_DSP2_MODULE
+ assign ddc_in_i = frontend_i;
+ assign ddc_in_q = frontend_q;
+ assign bb_sample = ddc_out_sample;
+ assign bb_strobe = ddc_out_strobe;
+ `else
+ RX_DSP2_CUSTOM_MODULE_NAME rx_dsp2_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
+ .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ else begin
+ `ifndef RX_DSP3_MODULE
+ assign ddc_in_i = frontend_i;
+ assign ddc_in_q = frontend_q;
+ assign bb_sample = ddc_out_sample;
+ assign bb_strobe = ddc_out_strobe;
+ `else
+ RX_DSP3_CUSTOM_MODULE_NAME rx_dsp3_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
+ .ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ endgenerate
+
+endmodule //custom_dsp_rx
diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v
new file mode 100644
index 000000000..102805139
--- /dev/null
+++ b/usrp2/custom/custom_dsp_tx.v
@@ -0,0 +1,139 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+//CUSTOMIZE ME!
+
+//The following module effects the IO of the DUC chain.
+//By default, this entire module is a simple pass-through.
+
+//To implement DSP logic before the DUC:
+//Implement custom DSP between baseband and duc input.
+
+//To implement DSP logic after the DUC:
+//Implement custom DSP between duc output and frontend.
+
+//To bypass the DUC with custom logic:
+//Implement custom DSP between baseband and frontend.
+
+module custom_dsp_tx
+#(
+ parameter DSPNO = 0,
+ parameter ADCW = 24
+)
+(
+ //control signals
+ input clock, input reset, input enable,
+
+ //settings bus
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ //full rate outputs directly to the TX frontend
+ output [ADCW-1:0] frontend_i,
+ output [ADCW-1:0] frontend_q,
+
+ //full rate outputs directly from the DUC chain
+ input [ADCW-1:0] duc_out_i,
+ input [ADCW-1:0] duc_out_q,
+
+ //strobed samples {I16,Q16} to the TX DUC chain
+ output [31:0] duc_in_sample,
+ input duc_in_strobe, //this is a backpressure signal
+
+ //strobbed baseband samples {I16,Q16} to this module
+ input [31:0] bb_sample,
+ output bb_strobe, //this is a backpressure signal
+
+ //debug output (optional)
+ output [31:0] debug
+);
+
+ generate
+ if (DSPNO==0) begin
+ `ifndef TX_DSP0_MODULE
+ assign frontend_i = duc_out_i;
+ assign frontend_q = duc_out_q;
+ assign duc_in_sample = bb_sample;
+ assign bb_strobe = duc_in_strobe;
+ `else
+ TX_DSP0_CUSTOM_MODULE_NAME tx_dsp0_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
+ .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ if (DSPNO==1) begin
+ `ifndef TX_DSP1_MODULE
+ assign frontend_i = duc_out_i;
+ assign frontend_q = duc_out_q;
+ assign duc_in_sample = bb_sample;
+ assign bb_strobe = duc_in_strobe;
+ `else
+ TX_DSP1_CUSTOM_MODULE_NAME tx_dsp1_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
+ .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ if (DSPNO==2) begin
+ `ifndef TX_DSP2_MODULE
+ assign frontend_i = duc_out_i;
+ assign frontend_q = duc_out_q;
+ assign duc_in_sample = bb_sample;
+ assign bb_strobe = duc_in_strobe;
+ `else
+ TX_DSP2_CUSTOM_MODULE_NAME tx_dsp2_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
+ .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ else begin
+ `ifndef TX_DSP3_MODULE
+ assign frontend_i = duc_out_i;
+ assign frontend_q = duc_out_q;
+ assign duc_in_sample = bb_sample;
+ assign bb_strobe = duc_in_strobe;
+ `else
+ TX_DSP3_CUSTOM_MODULE_NAME tx_dsp3_custom
+ (
+ .clock(clock), .reset(reset), .enable(enable),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .frontend_i(frontend_i), .frontend_q(frontend_q),
+ .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
+ .duc_in_sample(duc_in_sample), .duc_in_strobe(duc_in_strobe),
+ .bb_sample(bb_sample), .bb_strobe(bb_strobe)
+ );
+ `endif
+ end
+ endgenerate
+
+endmodule //custom_dsp_tx
diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v
index 02544a0fe..86ff2001b 100644
--- a/usrp2/sdr_lib/ddc_chain.v
+++ b/usrp2/sdr_lib/ddc_chain.v
@@ -18,9 +18,10 @@
//! The USRP digital down-conversion chain
module ddc_chain
- #(parameter BASE = 0)
+ #(parameter BASE = 0, parameter DSPNO = 0)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
// From RX frontend
input [23:0] rx_fe_i,
@@ -91,10 +92,12 @@ module ddc_chain
else
phase <= phase + phase_inc;
+ wire [23:0] to_cordic_i, to_cordic_q;
+
// CORDIC 24-bit I/O
cordic_z24 #(.bitwidth(25))
cordic(.clock(clk), .reset(rst), .enable(run),
- .xi({rx_fe_i_mux[23],rx_fe_i_mux}),. yi({rx_fe_q_mux[23],rx_fe_q_mux}), .zi(phase[31:8]),
+ .xi({to_cordic_i[23],to_cordic_i}),. yi({to_cordic_q[23],to_cordic_q}), .zi(phase[31:8]),
.xo(i_cordic),.yo(q_cordic),.zo() );
clip_reg #(.bits_in(25), .bits_out(24)) clip_i
@@ -136,12 +139,22 @@ module ddc_chain
.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
// Round final answer to 16 bits
+ wire [31:0] ddc_chain_out;
+ wire ddc_chain_stb;
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
- (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(sample[31:16]), .strobe_out(strobe));
+ (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(ddc_chain_out[31:16]), .strobe_out(ddc_chain_stb));
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
- (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(sample[15:0]), .strobe_out());
-
+ (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(ddc_chain_out[15:0]), .strobe_out());
+
+ custom_dsp_rx #(.DSPNO(DSPNO)) custom(
+ .clock(clk), .reset(rst), .enable(run),
+ .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+ .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux),
+ .ddc_in_i(to_cordic_i), .ddc_in_q(to_cordic_q),
+ .ddc_out_sample(ddc_chain_out), .ddc_out_strobe(ddc_chain_stb),
+ .bb_sample(sample), .bb_strobe(strobe));
+
assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
endmodule // ddc_chain
diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v
index 0d3ca258f..66d15d0ad 100644
--- a/usrp2/sdr_lib/duc_chain.v
+++ b/usrp2/sdr_lib/duc_chain.v
@@ -18,15 +18,16 @@
//! The USRP digital up-conversion chain
module duc_chain
- #(parameter BASE = 0)
+ #(parameter BASE = 0, parameter DSPNO = 0)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
- // From TX frontend
+ // To TX frontend
output [23:0] tx_fe_i,
output [23:0] tx_fe_q,
- // To TX control
+ // From TX control
input [31:0] sample,
input run,
output strobe,
@@ -85,8 +86,8 @@ module duc_chain
wire signed [17:0] da, db;
wire signed [35:0] prod_i, prod_q;
- wire [17:0] bb_i = {sample[31:16],2'b0};
- wire [17:0] bb_q = {sample[15:0],2'b0};
+ wire [15:0] bb_i;
+ wire [15:0] bb_q;
wire [17:0] i_interp, q_interp;
wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
@@ -96,9 +97,9 @@ module duc_chain
// but the default case inside hb_interp handles this
hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_i
- (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i));
+ (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_i, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_q
- (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q));
+ (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_q, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
small_hb_int #(.WIDTH(18)) small_hb_interp_i
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
@@ -148,9 +149,14 @@ module duc_chain
.R(rst) // Synchronous reset input
);
- assign tx_fe_i = prod_i[28:5];
- assign tx_fe_q = prod_q[28:5];
-
+ custom_dsp_tx #(.DSPNO(DSPNO)) custom(
+ .clock(clk), .reset(rst), .enable(run),
+ .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+ .frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
+ .duc_out_i(prod_i[28:5]), .duc_out_q(prod_q[28:5]),
+ .duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1),
+ .bb_sample(sample), .bb_strobe(strobe));
+
assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
endmodule // dsp_core
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 90dd25942..442b0b579 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -21,6 +21,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpif/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -50,7 +51,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPIF_SRCS)
+$(GPIF_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 64c8defb3..4cc9386ab 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -156,9 +156,10 @@ module u1plus_core
wire [35:0] vita_rx_data0;
wire vita_rx_src_rdy0, vita_rx_dst_rdy0;
- ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
@@ -179,9 +180,10 @@ module u1plus_core
wire [35:0] vita_rx_data1;
wire vita_rx_src_rdy1, vita_rx_dst_rdy1;
- ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
@@ -222,12 +224,13 @@ module u1plus_core
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.sample(sample_tx), .strobe(strobe_tx),
- .underrun(underrun), .run(run_tx),
+ .underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
- duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug() );
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 9b9a48911..397bac618 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpmc/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -53,7 +54,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPMC_SRCS)
+$(GPMC_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index be2761baf..1f95954ae 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpmc/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -53,7 +54,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPMC_SRCS)
+$(GPMC_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 2c3690b0a..9257e5541 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -161,9 +161,10 @@ module u1e_core
wire [35:0] vita_rx_data0;
wire vita_rx_src_rdy0, vita_rx_dst_rdy0;
- ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
@@ -184,9 +185,10 @@ module u1e_core
wire [35:0] vita_rx_data1;
wire vita_rx_src_rdy1, vita_rx_dst_rdy1;
- ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
@@ -227,10 +229,10 @@ module u1e_core
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.sample(sample_tx), .strobe(strobe_tx),
- .underrun(underrun), .run(run_tx),
+ .underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
- duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3
index 9ed5ece00..7181e7d62 100644
--- a/usrp2/top/N2x0/Makefile.N200R3
+++ b/usrp2/top/N2x0/Makefile.N200R3
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -52,7 +53,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4
index f8640224f..551f7a232 100644
--- a/usrp2/top/N2x0/Makefile.N200R4
+++ b/usrp2/top/N2x0/Makefile.N200R4
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -53,7 +54,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3
index 2937dc409..2514600f4 100644
--- a/usrp2/top/N2x0/Makefile.N210R3
+++ b/usrp2/top/N2x0/Makefile.N210R3
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -52,7 +53,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4
index 39a2508f9..951df0c7c 100644
--- a/usrp2/top/N2x0/Makefile.N210R4
+++ b/usrp2/top/N2x0/Makefile.N210R4
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -53,7 +54,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index bd9cbf610..63087842b 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -582,9 +582,10 @@ module u2plus_core
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
- ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
@@ -605,9 +606,10 @@ module u2plus_core
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
- ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
@@ -672,9 +674,10 @@ module u2plus_core
.clear_vita(clear_tx), //output internal vita clear signal
.debug(debug_vt));
- duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug() );
diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile
index 8ebb43639..adfaf06c4 100644
--- a/usrp2/top/USRP2/Makefile
+++ b/usrp2/top/USRP2/Makefile
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -52,7 +53,8 @@ u2_rev3.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index a83a68204..f2ca1908b 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -570,9 +570,10 @@ module u2_core
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
- ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
@@ -593,9 +594,10 @@ module u2_core
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
- ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
@@ -658,9 +660,10 @@ module u2_core
.clear_vita(clear_tx), //output internal vita clear signal
.debug(debug_vt));
- duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug() );
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 15:57:17 +0000