2 files changed, 31 insertions, 22 deletions

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index afba3428e..1b04c4f36 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -46,6 +46,10 @@ module dsp_core_rx
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
 
+   reg [17:0]  adc_i_mux, adc_q_mux;
+   wire        realmode;
+   wire        swap_iq;
+   
    setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -58,6 +62,22 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
+   setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({realmode,swap_iq}),.changed());
+
+   always @(posedge clk)
+     if(swap_iq)
+       begin
+	  adc_i_mux <= adc_q;
+	  adc_q_mux <= realmode ? 18'd0 : adc_i;
+       end
+     else
+       begin
+	  adc_i_mux <= adc_i;
+	  adc_q_mux <= realmode ? 18'd0 : adc_q;
+       end
+   
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -68,7 +88,7 @@ module dsp_core_rx
 
    MULT18X18S mult_i
      (.P(prod_i),    // 36-bit multiplier output
-      .A(adc_i),    // 18-bit multiplier input
+      .A(adc_i_mux),    // 18-bit multiplier input
       .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -77,7 +97,7 @@ module dsp_core_rx
 
    MULT18X18S mult_q
      (.P(prod_q),    // 36-bit multiplier output
-      .A(adc_q),    // 18-bit multiplier input
+      .A(adc_q_mux),    // 18-bit multiplier input
       .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index f93172f16..a95110240 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -14,31 +14,20 @@ module rx_frontend
    
    reg [15:0] 	  adc_i, adc_q;
    wire [17:0] 	  adc_i_ofs, adc_q_ofs;
-   wire [35:0] 	  corr_i, corr_q;
-   wire [17:0] 	  mag_corr,phase_corr;
-   wire [7:0] 	  muxctrl;
+   wire [35:0] 	  corr_i, corr_q; wire [17:0] 	  mag_corr,phase_corr;
+   wire 	  swap_iq;
    wire [23:0] 	  i_final, q_final;
    
-   setting_reg #(.my_addr(BASE), .width(8)) sr_8
+   setting_reg #(.my_addr(BASE), .width(1)) sr_8
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(muxctrl),.changed());
+      .in(set_data),.out(swap_iq),.changed());
 
    always @(posedge clk)
-     case(muxctrl[3:0])		// The I mapping
-       0: adc_i <= adc_a;
-       1: adc_i <= adc_b;
-       2: adc_i <= 0;
-       default: adc_i <= 0;
-     endcase // case (muxctrl[3:0])
-   
-   always @(posedge clk)
-     case(muxctrl[7:4])		// The Q mapping
-       0: adc_q <= adc_a;
-       1: adc_q <= adc_b;
-       2: adc_q <= 0;
-       default: adc_q <= 0;
-     endcase // case (muxctrl[7:4])
-   
+     if(swap_iq) // Swap
+       {adc_i,adc_q} <= {adc_b,adc_a};
+     else
+       {adc_i,adc_q} <= {adc_a,adc_b};
+       
    setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(mag_corr),.changed());