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-rw-r--r--usrp2/control_lib/Makefile.srcs1
-rw-r--r--usrp2/control_lib/ram_harvard.v69
-rw-r--r--usrp2/control_lib/ram_loader.v460
-rw-r--r--usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v5
-rw-r--r--usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v27
-rwxr-xr-x[-rw-r--r--]usrp2/top/u2_rev3/u2_core.v50
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v53
7 files changed, 390 insertions, 275 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index 5e2a96a53..bc8e4d5bc 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -20,6 +20,7 @@ mux8.v \
nsgpio.v \
ram_2port.v \
ram_harv_cache.v \
+ram_harvard.v \
ram_loader.v \
setting_reg.v \
settings_bus.v \
diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v
new file mode 100644
index 000000000..948f9b36f
--- /dev/null
+++ b/usrp2/control_lib/ram_harvard.v
@@ -0,0 +1,69 @@
+
+
+// Dual ported, Harvard architecture, cached ram
+
+module ram_harvard
+ #(parameter AWIDTH=15,
+ parameter RAM_SIZE=16384,
+ parameter ICWIDTH=6,
+ parameter DCWIDTH=6)
+
+ (input wb_clk_i,
+ input wb_rst_i,
+ // Firmware download port.
+ input [AWIDTH-1:0] ram_loader_adr_i,
+ input [31:0] ram_loader_dat_i,
+ input [3:0] ram_loader_sel_i,
+ input ram_loader_stb_i,
+ input ram_loader_we_i,
+ input ram_loader_done_i,
+ // Instruction fetch port.
+ input [AWIDTH-1:0] if_adr,
+ output [31:0] if_data,
+ // Data access port.
+ input [AWIDTH-1:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i,
+
+ input flush_icache );
+
+ reg ack_d1;
+ reg stb_d1;
+
+ dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE))
+ sys_ram
+ (.clk(wb_clk_i),
+ .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i),
+ .dat1_i(ram_loader_dat_i),
+ .dat1_o(if_data),
+ .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
+ .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i),
+ //.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
+ .sel1_i(ram_loader_sel_i), // Sel is only for writes anyway
+ .adr2_i(dwb_adr_i),
+ .dat2_i(dwb_dat_i),
+ .dat2_o(dwb_dat_o),
+ .we2_i(dwb_we_i),
+ .en2_i(dwb_stb_i),
+ .sel2_i(dwb_sel_i)
+ );
+
+ assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ ack_d1 <= 1'b0;
+ else
+ ack_d1 <= dwb_ack_o;
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ stb_d1 <= 0;
+ else
+ stb_d1 <= dwb_stb_i;
+
+endmodule // ram_harvard
diff --git a/usrp2/control_lib/ram_loader.v b/usrp2/control_lib/ram_loader.v
index cb67de739..c53ea7aa7 100644
--- a/usrp2/control_lib/ram_loader.v
+++ b/usrp2/control_lib/ram_loader.v
@@ -1,225 +1,261 @@
+module ram_loader
+ #(parameter AWIDTH=16, RAM_SIZE=16384)
+ (
+ // Wishbone I/F and clock domain
+ input wb_clk,
+ input dsp_clk,
+ input ram_loader_rst,
+ output wire [31:0] wb_dat,
+ output wire [AWIDTH-1:0] wb_adr,
+ output wb_stb,
+ output reg [3:0] wb_sel,
+ output wb_we,
+ output reg ram_loader_done,
+ // CPLD signals and clock domain
+ input cpld_clk,
+ input cpld_din,
+ output reg cpld_start,
+ output reg cpld_mode,
+ output reg cpld_done,
+ input cpld_detached
+ );
-// Adapted from VHDL code in spi_boot by Arnim Legauer
-// Added a full wishbone master interface (32-bit)
-
-module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384)
- (input clk_i, input rst_i,
- // CPLD Interface
- input cfg_clk_i, input cfg_data_i,
- output start_o, output mode_o, output done_o,
- input detached_i,
- // Wishbone interface
- output wire [31:0] wb_dat_o,
- output reg [AWIDTH-1:0] wb_adr_o,
- output wb_stb_o,
- output wb_cyc_o,
- output reg [3:0] wb_sel_o,
- output reg wb_we_o,
- input wb_ack_i,
- output ram_loader_done_o);
+ localparam S0 = 0;
+ localparam S1 = 1;
+ localparam S2 = 2;
+ localparam S3 = 3;
+ localparam S4 = 4;
+ localparam S5 = 5;
+ localparam S6 = 6;
+ localparam RESET = 7;
- // FSM to control start signal, clocked on main clock
- localparam FSM1_WAIT_DETACH = 2'b00;
- localparam FSM1_CHECK_NO_DONE = 2'b01;
- localparam FSM1_WAIT_DONE = 2'b10;
-
- reg [1:0] start_fsm_q, start_fsm_s;
- reg start_q, enable_q, start_s, enable_s;
- reg done_q, done_s;
+ localparam WB_IDLE = 0;
+ localparam WB_WRITE = 1;
+
+
+ reg [AWIDTH+2:0] count; // 3 LSB's count bits in, the MSB's generate the Wishbone address
+ reg [6:0] shift_reg;
+ reg [7:0] data_reg;
+ reg sampled_clk;
+ reg sampled_clk_meta;
+ reg sampled_din;
+ reg inc_count;
+ reg load_data_reg;
+ reg shift;
+ reg wb_state, wb_next_state;
+ reg [2:0] state, next_state;
+
+ //
+ // CPLD clock doesn't free run and is approximately 12.5MHz.
+ // Use 50MHz Wishbone clock to sample it as a signal and avoid having
+ // an extra clock domain for no reason.
+ //
+
+ always @(posedge dsp_clk or posedge ram_loader_rst)
+ if (ram_loader_rst)
+ begin
+ sampled_clk_meta <= 1'b0;
+ sampled_clk <= 1'b0;
+ sampled_din <= 1'b0;
+ count <= 'h7FFF8; // Initialize so that address will be 0 when first byte fully received.
+ data_reg <= 0;
+ shift_reg <= 0;
+ end
+ else
+ begin
+ sampled_clk_meta <= cpld_clk;
+ sampled_clk <= sampled_clk_meta;
+ sampled_din <= cpld_din;
+ if (inc_count)
+ count <= count + 1'b1;
+ if (load_data_reg)
+ data_reg <= {shift_reg,sampled_din};
+ if (shift)
+ shift_reg <= {shift_reg[5:0],sampled_din};
+ end // else: !if(ram_loader_rst)
- always @(posedge clk_i or posedge rst_i)
- if(rst_i)
- begin
- start_fsm_q <= FSM1_WAIT_DETACH;
- start_q <= 1'b0;
- enable_q <= 1'b0;
- end
+
+ always @(posedge dsp_clk or posedge ram_loader_rst)
+ if (ram_loader_rst)
+ state <= RESET;
else
- begin
- start_fsm_q <= start_fsm_s;
- enable_q <= enable_s;
- start_q <= start_s;
- end // else: !if(rst_i)
-
+ state <= next_state;
+
+
always @*
- case(start_fsm_q)
- FSM1_WAIT_DETACH:
- if(detached_i == 1'b1)
- begin
- start_fsm_s <= FSM1_CHECK_NO_DONE;
- enable_s <= 1'b1;
- start_s <= 1'b1;
- end
- else
- begin
- start_fsm_s <= FSM1_WAIT_DETACH;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(detached_i == 1'b1)
- FSM1_CHECK_NO_DONE:
- if(~done_q)
- begin
- start_fsm_s <= FSM1_WAIT_DONE;
- enable_s <= enable_q;
- start_s <= start_q;
- end
- else
- begin
- start_fsm_s <= FSM1_CHECK_NO_DONE;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(~done_q)
- FSM1_WAIT_DONE:
- if(done_q)
- begin
- start_fsm_s <= FSM1_WAIT_DETACH;
- enable_s <= 1'b0;
- start_s <= 1'b0;
- end
- else
- begin
- start_fsm_s <= FSM1_WAIT_DONE;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(done_q)
- default:
- begin
- start_fsm_s <= FSM1_WAIT_DETACH;
- enable_s <= enable_q;
- start_s <= start_q;
- end // else: !if(done_q)
- endcase // case(start_fsm_q)
-
- // FSM running on data clock
-
- localparam FSM2_IDLE = 3'b000;
- localparam FSM2_WE_ON = 3'b001;
- localparam FSM2_WE_OFF = 3'b010;
- localparam FSM2_INC_ADDR1 = 3'b011;
- localparam FSM2_INC_ADDR2 = 3'b100;
- localparam FSM2_FINISHED = 3'b101;
-
- reg [AWIDTH-1:0] addr_q;
- reg [7:0] shift_dat_q, ser_dat_q;
- reg [2:0] bit_q, fsm_q, fsm_s;
- reg bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, inc_addr_s;
-
- always @(posedge cfg_clk_i or posedge rst_i)
- if(rst_i)
- begin
- addr_q <= 0;
- shift_dat_q <= 8'd0;
- ser_dat_q <= 8'd0;
- bit_q <= 3'd0;
- bit_ovfl_q <= 1'b0;
- fsm_q <= FSM2_IDLE;
- ram_we_q <= 1'b0;
- done_q <= 1'b0;
- mode_q <= 1'b0;
- end
+ begin
+ // Defaults
+ next_state = state;
+ cpld_start = 1'b0;
+ shift = 1'b0;
+ inc_count = 0;
+ load_data_reg = 1'b0;
+ ram_loader_done = 1'b0;
+ cpld_mode = 1'b0;
+ cpld_done = 1'b1;
+
+
+
+ case (state) //synthesis parallel_case full_case
+ // After reset wait until CPLD indicates its detached.
+ RESET: begin
+ if (cpld_detached)
+ next_state = S0;
+ else
+ next_state = RESET;
+ end
+
+ // Assert cpld_start to signal the CPLD its to start sending serial clock and data.
+ // Assume cpld_clk is low as we transition into search for first rising edge
+ S0: begin
+ cpld_start = 1'b1;
+ cpld_done = 1'b0;
+ if (~cpld_detached)
+ next_state = S2;
+ else
+ next_state = S0;
+ end
+
+ //
+ S1: begin
+ cpld_start = 1'b1;
+ cpld_done = 1'b0;
+ if (sampled_clk)
+ begin
+ // Found rising edge on cpld_clk.
+ if (count[2:0] == 3'b111)
+ // Its the last bit of a byte, send it out to the Wishbone bus.
+ begin
+ load_data_reg = 1'b1;
+ inc_count = 1'b1;
+ end
+ else
+ // Shift databit into LSB of shift register and increment count
+ begin
+ shift = 1'b1;
+ inc_count = 1'b1;
+ end // else: !if(count[2:0] == 3'b111)
+ next_state = S2;
+ end // if (sampled_clk)
+ else
+ next_state = S1;
+ end // case: S1
+
+ //
+ S2: begin
+ cpld_start = 1'b1;
+ cpld_done = 1'b0;
+ if (~sampled_clk)
+ // Found negative edge of clock
+ if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant
+ // All firmware now downloaded
+ next_state = S3;
+ else
+ next_state = S1;
+ else
+ next_state = S2;
+ end // case: S2
+
+ // Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done
+ // and that mode is now SPI mode.
+ S3: begin
+ if (sampled_clk)
+ begin
+ cpld_mode = 1'b1;
+ cpld_done = 1'b1;
+ next_state = S4;
+ end
+ else
+ next_state = S3;
+ end
+
+ // Search for negedge of cpld_clk whilst keeping done sequence asserted.
+ // Keep done assserted
+ S4: begin
+ cpld_mode = 1'b1;
+ cpld_done = 1'b1;
+ if (~sampled_clk)
+ next_state = S5;
+ else
+ next_state = S4;
+ end
+
+ // Search for posedge of cpld_clk whilst keeping done sequence asserted.
+ S5: begin
+ cpld_mode = 1'b1;
+ cpld_done = 1'b1;
+ if (sampled_clk)
+ next_state = S6;
+ else
+ next_state = S5;
+ end
+
+ // Stay in this state until reset/power down
+ S6: begin
+ ram_loader_done = 1'b1;
+ cpld_done = 1'b1;
+ cpld_mode = 1'b1;
+ next_state = S6;
+ end
+
+ endcase // case(state)
+ end
+
+ always @(posedge dsp_clk or posedge ram_loader_rst)
+ if (ram_loader_rst)
+ wb_state <= WB_IDLE;
else
- begin
- if(inc_addr_s)
- addr_q <= addr_q + 1;
- if(enable_q)
- begin
- bit_q <= bit_q + 1;
- bit_ovfl_q <= (bit_q == 3'd7);
- shift_dat_q[0] <= cfg_data_i;
- shift_dat_q[7:1] <= shift_dat_q[6:0];
- end
- if(bit_ovfl_q)
- ser_dat_q <= shift_dat_q;
-
- fsm_q <= fsm_s;
-
- ram_we_q <= ram_we_s;
-
- if(done_s)
- done_q <= 1'b1;
- mode_q <= mode_s;
- end // else: !if(rst_i)
+ wb_state <= wb_next_state;
+ reg do_write;
+ wire empty, full;
+
always @*
begin
- inc_addr_s <= 1'b0;
- ram_we_s <= 1'b0;
- done_s <= 1'b0;
- fsm_s <= FSM2_IDLE;
- mode_s <= 1'b0;
-
- case(fsm_q)
- FSM2_IDLE :
- if(start_q)
- if(bit_ovfl_q)
- fsm_s <= FSM2_WE_ON;
- FSM2_WE_ON:
- begin
- ram_we_s <= 1'b1;
- fsm_s <= FSM2_WE_OFF;
- end
- FSM2_WE_OFF:
- begin
- ram_we_s <= 1'b1;
- fsm_s <= FSM2_INC_ADDR1;
- end
- FSM2_INC_ADDR1:
- fsm_s <= FSM2_INC_ADDR2;
- FSM2_INC_ADDR2:
- if(addr_q == (RAM_SIZE-1))
- //if(&addr_q)
- begin
- fsm_s <= FSM2_FINISHED;
- done_s <= 1'b1;
- mode_s <= 1'b1;
- end
- else
- begin
- inc_addr_s <= 1'b1;
- fsm_s <= FSM2_IDLE;
- end // else: !if(&addr_q)
- FSM2_FINISHED:
- begin
- fsm_s <= FSM2_FINISHED;
- mode_s <= 1'b1;
- end
- endcase // case(fsm_q)
+ wb_next_state = wb_state;
+ do_write = 1'b0;
+
+ case (wb_state) //synthesis full_case parallel_case
+ //
+ WB_IDLE: begin
+ if (load_data_reg)
+ // Data reg will load ready to write wishbone @ next clock edge
+ wb_next_state = WB_WRITE;
+ else
+ wb_next_state = WB_IDLE;
+ end
+
+ // Drive address and data onto wishbone.
+ WB_WRITE: begin
+ do_write = 1'b1;
+ if (~full)
+ wb_next_state = WB_IDLE;
+ else
+ wb_next_state = WB_WRITE;
+ end
+
+ endcase // case(wb_state)
end // always @ *
- assign start_o = start_q;
- assign mode_o = mode_q;
- assign done_o = start_q ? done_q : 1'b1;
- wire [AWIDTH-1:0] ram_addr = addr_q;
- wire [7:0] ram_data = ser_dat_q;
- assign ram_loader_done_o = (fsm_q == FSM2_FINISHED);
-
- // wishbone master, only writes
- reg [7:0] dat_holder;
- assign wb_dat_o = {4{dat_holder}};
- assign wb_stb_o = wb_we_o;
- assign wb_cyc_o = wb_we_o;
+ wire [1:0] count_out;
+ wire [7:0] data_out;
+
+ fifo_xlnx_16x40_2clk crossclk
+ (.rst(ram_loader_rst),
+ .wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full),
+ .rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty));
+
+ assign wb_dat = {4{data_out}};
+
+ always @*
+ case(count_out[1:0]) //synthesis parallel_case full_case
+ 2'b00 : wb_sel = 4'b1000;
+ 2'b01 : wb_sel = 4'b0100;
+ 2'b10 : wb_sel = 4'b0010;
+ 2'b11 : wb_sel = 4'b0001;
+ endcase
+
+ assign wb_we = ~empty;
+ assign wb_stb = ~empty;
- always @(posedge clk_i or posedge rst_i)
- if(rst_i)
- begin
- dat_holder <= 8'd0;
- wb_adr_o <= 0;
- wb_sel_o <= 4'b0000;
- wb_we_o <= 1'b0;
- end
- else if(ram_we_q)
- begin
- dat_holder <= ram_data;
- wb_adr_o <= ram_addr;
- wb_we_o <= 1'b1;
- case(ram_addr[1:0]) // Big Endian
- 2'b00 : wb_sel_o <= 4'b1000;
- 2'b01 : wb_sel_o <= 4'b0100;
- 2'b10 : wb_sel_o <= 4'b0010;
- 2'b11 : wb_sel_o <= 4'b0001;
- endcase // case(ram_addr[1:0])
- end // if (ram_we_q)
- else if(wb_ack_i)
- wb_we_o <= 1'b0;
-
endmodule // ram_loader
diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
index a7c686e7e..81587e25c 100644
--- a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
+++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
@@ -125,7 +125,7 @@ module aeMB_bpcu (/*AUTOARG*/
reg [31:2] rPC, xPC;
reg [31:2] rPCLNK, xPCLNK;
- assign iwb_adr_o = rIPC[IW-1:2];
+ assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB
always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin
//xPCLNK <= (^rATOM) ? rPC : rPC;
@@ -168,7 +168,8 @@ module aeMB_bpcu (/*AUTOARG*/
rATOM <= 2'h0;
rBRA <= 1'h0;
rDLY <= 1'h0;
- rIPC <= 30'h0;
+// rIPC <= 30'h0;
+ rIPC <= 30'h3fffffff; // DWORD aligned address
rPC <= 30'h0;
rPCLNK <= 30'h0;
// End of automatics
diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
index 9ffa20ff2..38ca3a023 100644
--- a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
+++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
@@ -10,12 +10,10 @@ module aeMB_core_BE
parameter MUL=0, parameter BSF=0)
(input sys_clk_i,
input sys_rst_i,
-
- output iwb_stb_o,
- output [ISIZ-1:0] iwb_adr_o,
- input [31:0] iwb_dat_i,
- input iwb_ack_i,
-
+ // Instruction port
+ output [14:0] if_adr,
+ input [31:0] if_dat,
+ // Data port
output dwb_we_o,
output dwb_stb_o,
output [DSIZ-1:0] dwb_adr_o,
@@ -28,17 +26,28 @@ module aeMB_core_BE
input sys_int_i,
input sys_exc_i);
- assign dwb_cyc_o = dwb_stb_o;
+ wire [ISIZ-1:0] iwb_adr_o;
+ wire [31:0] iwb_dat_i;
+ wire iwb_ack_i;
+ wire iwb_stb_o;
+
+ assign dwb_cyc_o = dwb_stb_o;
+ assign iwb_ack_i = 1'b1;
+ assign if_adr = iwb_adr_o[14:0];
+ assign iwb_dat_i = if_dat;
+
+ // Note some "wishbone" instruction fetch signals pruned on external interface
+ // but not propogated change deep into aeMB.
aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
aeMB_edk32 (.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
-
+ // Instruction Port
.iwb_stb_o(iwb_stb_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i),
-
+ // Data port
.dwb_wre_o(dwb_we_o),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index b67d8edd6..9ba3cc136 100644..100755
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -277,33 +277,33 @@ module u2_core
// ///////////////////////////////////////////////////////////////////
// RAM Loader
- wire [31:0] ram_loader_dat, iwb_dat;
- wire [15:0] ram_loader_adr, iwb_adr;
+ wire [31:0] ram_loader_dat, if_dat;
+ wire [15:0] ram_loader_adr;
+ wire [14:0] if_adr;
wire [3:0] ram_loader_sel;
- wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire ram_loader_stb, ram_loader_we;
wire iwb_ack, iwb_stb;
ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
- ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+ .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+ .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+ .wb_we(ram_loader_we),
+ .ram_loader_done(ram_loader_done),
// CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start_int),
- .mode_o(cpld_mode_int),
- .done_o(cpld_done_int),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
- .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
- .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
- .ram_loader_done_o(ram_loader_done));
-
+ .cpld_clk(cpld_clk),
+ .cpld_din(cpld_din),
+ .cpld_start(cpld_start_int),
+ .cpld_mode(cpld_mode_int),
+ .cpld_done(cpld_done_int),
+ .cpld_detached(cpld_detached));
+
// /////////////////////////////////////////////////////////////////////////
// Processor
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .if_adr(if_adr),
+ .if_dat(if_dat),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -317,16 +317,16 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
- .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
- .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+ .if_adr(if_adr),
+ .if_data(if_dat),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -622,7 +622,7 @@ module u2_core
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
-
+/*
localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes
wire [15:0] bus2ram, ram2bus;
@@ -650,6 +650,7 @@ module u2_core
.sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
.sram_mode(),.sram_zz() );
+*/
assign RAM_CE1n = 0;
assign RAM_D[17:16] = 2'bzz;
@@ -700,7 +701,8 @@ module u2_core
{ wr2_flags, rd2_flags },
{ GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
- assign debug_gpio_0 = debug_mac; //eth_mac_debug;
+ assign debug_gpio_0 = 0;
+ //debug_mac; //eth_mac_debug;
assign debug_gpio_1 = 0;
endmodule // u2_core
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index cb0ed78c7..798022adc 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -279,33 +279,33 @@ module u2_core
// ///////////////////////////////////////////////////////////////////
// RAM Loader
- wire [31:0] ram_loader_dat, iwb_dat;
- wire [15:0] ram_loader_adr, iwb_adr;
+ wire [31:0] ram_loader_dat, if_dat;
+ wire [15:0] ram_loader_adr;
+ wire [14:0] if_adr;
wire [3:0] ram_loader_sel;
- wire ram_loader_stb, ram_loader_we, ram_loader_ack;
+ wire ram_loader_stb, ram_loader_we;
wire iwb_ack, iwb_stb;
ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
- ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+ ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+ .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+ .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+ .wb_we(ram_loader_we),
+ .ram_loader_done(ram_loader_done),
// CPLD Interface
- .cfg_clk_i(cpld_clk),
- .cfg_data_i(cpld_din),
- .start_o(cpld_start_int),
- .mode_o(cpld_mode_int),
- .done_o(cpld_done_int),
- .detached_i(cpld_detached),
- // Wishbone Interface
- .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
- .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
- .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
- .ram_loader_done_o(ram_loader_done));
-
+ .cpld_clk(cpld_clk),
+ .cpld_din(cpld_din),
+ .cpld_start(cpld_start_int),
+ .cpld_mode(cpld_mode_int),
+ .cpld_done(cpld_done_int),
+ .cpld_detached(cpld_detached));
+
// /////////////////////////////////////////////////////////////////////////
// Processor
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
// Instruction Wishbone bus to I-RAM
- .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
- .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+ .if_adr(if_adr),
+ .if_dat(if_dat),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -319,16 +319,16 @@ module u2_core
// I-port connects directly to processor and ram loader
wire flush_icache;
- ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
- .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+ .ram_loader_we_i(ram_loader_we),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
- .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+ .if_adr(if_adr),
+ .if_data(if_dat),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -773,8 +773,7 @@ endmodule // u2_core
{ s6_adr[15:8] },
{ s6_adr[7:0] },
{ 6'd0, mdio_cpy, MDC } };
-*/
-/*
+
assign debug = { { GMII_TXD },
{ 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
{ wr2_flags, rd2_flags },
@@ -783,7 +782,6 @@ endmodule // u2_core
{ 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
{ wr2_flags, rd2_flags },
{ GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
- */
// assign debug = debug_udp;
// assign debug = vrc_debug;
@@ -794,9 +792,8 @@ endmodule // u2_core
{wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}};
*/
// assign debug_gpio_1 = {vita_time[63:32] };
-
-/*
- assign debug_gpio_1 = { { tx_f19_data[15:8] },
+/*
+ assign debug_gpio_1 = { { tx_f19_data[15:8] },
{ tx_f19_data[7:0] },
{ 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
{ 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 16:50:54 +0000