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-rwxr-xr-xusrp2/top/B100/core_compile1
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile
new file mode 100755
index 000000000..b2ccc8b49
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+iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models