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-rw-r--r--usrp2/control_lib/setting_reg.v8
1 files changed, 5 insertions, 3 deletions
diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v
index ccbaa3d2e..3d3bb65e5 100644
--- a/usrp2/control_lib/setting_reg.v
+++ b/usrp2/control_lib/setting_reg.v
@@ -1,14 +1,16 @@
module setting_reg
- #(parameter my_addr = 0)
+ #(parameter my_addr = 0,
+ parameter width = 32,
+ parameter at_reset=32'd0)
(input clk, input rst, input strobe, input wire [7:0] addr,
- input wire [31:0] in, output reg [31:0] out, output reg changed);
+ input wire [31:0] in, output reg [width-1:0] out, output reg changed);
always @(posedge clk)
if(rst)
begin
- out <= 32'd0;
+ out <= at_reset;
changed <= 1'b0;
end
else