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-rw-r--r--usrp2/control_lib/nsgpio16LE.v124
-rw-r--r--usrp2/control_lib/ram_2port_mixed_width.v44
-rw-r--r--usrp2/control_lib/settings_bus_16LE.v54
-rw-r--r--usrp2/control_lib/simple_uart.v13
-rw-r--r--usrp2/gpmc/gpmc.v81
-rw-r--r--usrp2/models/gpmc_model.v74
-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_clgen.v20
-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_defines.v8
-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_shift.v90
-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_top.v68
-rw-r--r--usrp2/top/safe_u1e/.gitignore4
-rw-r--r--usrp2/top/safe_u1e/Makefile246
-rw-r--r--usrp2/top/safe_u1e/safe_u1e.ucf262
-rw-r--r--usrp2/top/safe_u1e/safe_u1e.v41
-rw-r--r--usrp2/top/u1e/.gitignore6
-rw-r--r--usrp2/top/u1e/Makefile248
-rw-r--r--usrp2/top/u1e/README4
-rw-r--r--usrp2/top/u1e/cmdfile20
-rw-r--r--usrp2/top/u1e/make.sim7
-rw-r--r--usrp2/top/u1e/tb_u1e.v36
-rw-r--r--usrp2/top/u1e/u1e.ucf260
-rw-r--r--usrp2/top/u1e/u1e.v34
-rw-r--r--usrp2/top/u1e/u1e_core.v214
23 files changed, 1856 insertions, 102 deletions
diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..6847bb4a9
--- /dev/null
+++ b/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,124 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// OpenCores Simple General Purpose IO core ////
+//// ////
+//// Author: Richard Herveille ////
+//// richard@asics.ws ////
+//// www.asics.ws ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2002 Richard Herveille ////
+//// richard@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+ (input clk_i, input rst_i,
+ input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i,
+ output reg [15:0] dat_o, output reg ack_o,
+ input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1,
+ inout [31:0] gpio
+ );
+
+ reg [63:0] ctrl;
+ reg [31:0] line;
+ reg [31:0] lgpio; // LatchedGPIO pins
+ reg [31:0] ddr;
+
+ wire wb_acc = cyc_i & stb_i; // WISHBONE access
+ wire wb_wr = wb_acc & we_i; // WISHBONE write access
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i)
+ begin
+ ctrl <= 64'h0;
+ line <= 0;
+ end
+ else if (wb_wr)
+ case( adr_i[3:1] )
+ 3'b000 :
+ line[15:0] <= dat_i;
+ 3'b001 :
+ line[31:16] <= dat_i;
+ 3'b010 :
+ ddr[15:0] <= dat_i;
+ 3'b011 :
+ ddr[31:16] <= dat_i;
+ 3'b100 :
+ ctrl[15:0] <= dat_i;
+ 3'b101 :
+ ctrl[31:16] <= dat_i;
+ 3'b110 :
+ ctrl[47:32] <= dat_i;
+ 3'b111 :
+ ctrl[63:48] <= dat_i;
+ endcase // case ( adr_i[3:1] )
+
+ always @(posedge clk_i)
+ case (adr_i[3:1])
+ 3'b000 :
+ dat_o <= lgpio[15:0];
+ 3'b001 :
+ dat_o <= lgpio[31:16];
+ 3'b010 :
+ dat_o <= ddr[15:0];
+ 3'b011 :
+ dat_o <= ddr[31:16];
+ 3'b100 :
+ dat_o <= ctrl[15:0];
+ 3'b101 :
+ dat_o <= ctrl[31:16];
+ 3'b110 :
+ dat_o <= ctrl[47:32];
+ 3'b111 :
+ dat_o <= ctrl[63:48];
+ endcase // case (adr_i[3:1])
+
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i)
+ ack_o <= 1'b0;
+ else
+ ack_o <= wb_acc & !ack_o;
+
+ // latch GPIO input pins
+ always @(posedge clk_i)
+ lgpio <= gpio;
+
+ // assign GPIO outputs
+ integer n;
+ reg [31:0] igpio; // temporary internal signal
+
+ always @(ctrl or line or debug_1 or debug_0 or atr)
+ for(n=0;n<32;n=n+1)
+ igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) :
+ (ctrl[2*n] ? atr[n] : line[n]) )
+ : 1'bz;
+
+ assign gpio = igpio;
+
+endmodule
+
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..3fa43114f
--- /dev/null
+++ b/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,44 @@
+
+
+module ram_2port_mixed_width
+ #(parameter AWIDTH=9)
+ (input clk16,
+ input en16,
+ input we16,
+ input [10:0] addr16,
+ input [15:0] di16,
+ output reg [15:0] do16,
+
+ input clk32,
+ input en32,
+ input we32,
+ input [9:0] addr32,
+ input [31:0] di32,
+ output reg [31:0] do32);
+
+ reg [31:0] ram [(1<<AWIDTH)-1:0];
+ integer i;
+ initial
+ for(i=0;i<512;i=i+1)
+ ram[i] <= 32'b0;
+
+ always @(posedge clk16)
+ if (en16)
+ begin
+ if (we16)
+ if(addr16[0])
+ ram[addr16[10:1]][15:0] <= di16;
+ else
+ ram[addr16[10:1]][31:16] <= di16;
+ do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+ end
+
+ always @(posedge clk32)
+ if (en32)
+ begin
+ if (we32)
+ ram[addr32] <= di32;
+ do32 <= ram[addr32];
+ end
+
+endmodule // ram_2port_mixed_width
diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..fbef9b1c9
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+ #(parameter AWIDTH=16)
+ (input wb_clk,
+ input wb_rst,
+ input [AWIDTH-1:0] wb_adr_i,
+ input [15:0] wb_dat_i,
+ input wb_stb_i,
+ input wb_we_i,
+ output reg wb_ack_o,
+ output strobe,
+ output reg [7:0] addr,
+ output reg [31:0] data);
+
+ reg stb_int;
+
+ always @(posedge wb_clk)
+ if(wb_rst)
+ begin
+ stb_int <= 1'b0;
+ addr <= 8'd0;
+ data <= 32'd0;
+ end
+ else if(wb_we_i & wb_stb_i)
+ begin
+ addr <= wb_adr_i[9:2];
+ if(wb_adr_i[1])
+ begin
+ stb_int <= 1'b1; // We now have both halves
+ data[31:16] <= wb_dat_i;
+ end
+ else
+ begin
+ stb_int <= 1'b0; // Don't strobe, we need other half
+ data[15:0] <= wb_dat_i;
+ end
+ end
+ else
+ stb_int <= 1'b0;
+
+ always @(posedge wb_clk)
+ if(wb_rst)
+ wb_ack_o <= 0;
+ else
+ wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+ assign strobe = stb_int & wb_ack_o;
+
+endmodule // settings_bus_16LE
diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/usrp2/control_lib/simple_uart.v
+++ b/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
module simple_uart
#(parameter TXDEPTH = 1,
- parameter RXDEPTH = 1)
- (input clk_i, input rst_i,
- input we_i, input stb_i, input cyc_i, output reg ack_o,
- input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
- output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+ parameter RXDEPTH = 1,
+ parameter CLKDIV_DEFAULT = 16'd0)
+ (input clk_i, input rst_i,
+ input we_i, input stb_i, input cyc_i, output reg ack_o,
+ input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+ output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
// Register Map
localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
always @(posedge clk_i)
if (rst_i)
- clkdiv <= 0;
+ clkdiv <= CLKDIV_DEFAULT;
else if (wb_wr)
case(adr_i)
SUART_CLKDIV : clkdiv <= dat_i[15:0];
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
new file mode 100644
index 000000000..88f6809f8
--- /dev/null
+++ b/usrp2/gpmc/gpmc.v
@@ -0,0 +1,81 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc
+ (// GPMC signals
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+
+ // Wishbone signals
+ input wb_clk, input wb_rst,
+ output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+ output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i,
+
+ // RAM Interface signals
+ input ram_clk,
+ input read_en, input read_sel, input [8:0] read_addr, output [31:0] read_data, output read_rdy,
+ input write_en, input write_sel, input [8:0] write_addr, input [31:0] write_data, output write_rdy
+ );
+
+ wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+ wire [15:0] EM_D_ram;
+ wire [15:0] EM_D_wb;
+
+ assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb;
+
+ // CS4 is RAM_2PORT for high-speed data
+ // Writes go into one RAM, reads come from the other
+
+ ram_2port_mixed_width buffer_from_host
+ (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({store_pg,EM_A}), .di16(EM_D), .do16(),
+ .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel,read_addr}), .di32(0), .do32(read_data));
+
+ ram_2port_mixed_width buffer_to_host
+ (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({retr_page,EM_A}), .di16(0), .do16(EM_D_ram),
+ .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel,write_addr}), .di32(write_data), .do32());
+
+ // CS6 is Control, Wishbone bus bridge (wb master)
+ // Sync version
+ reg [1:0] cs_del, we_del, oe_del;
+
+ // Synchronize the async control signals
+ always @(posedge wb_clk)
+ begin
+ cs_del <= { cs_del[0], EM_NCS6 };
+ we_del <= { we_del[0], EM_NWE };
+ oe_del <= { oe_del[0], EM_NOE };
+ end
+
+ always @(posedge wb_clk)
+ if(cs_del == 2'b10) // Falling Edge
+ wb_adr_o <= { EM_A, 1'b0 };
+
+ always @(posedge wb_clk)
+ if(we_del == 2'b10) // Falling Edge
+ begin
+ wb_dat_mosi <= EM_D;
+ wb_sel_o <= ~EM_NBE;
+ end
+
+ reg [15:0] EM_D_wb_reg;
+ always @(posedge wb_clk)
+ if(wb_ack_i)
+ EM_D_wb_reg <= wb_dat_miso;
+
+ assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg;
+
+ assign wb_cyc_o = wb_stb_o;
+
+ always @(posedge wb_clk)
+ if( ~cs_del[0] & (we_del == 2'b10) )
+ wb_we_o <= 1;
+ else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others...
+ wb_we_o <= 0;
+
+ always @(posedge wb_clk)
+ if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+ wb_stb_o <= 1;
+ else if(wb_ack_i)
+ wb_stb_o <= 0;
+
+endmodule // gpmc
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
new file mode 100644
index 000000000..38dde1fa5
--- /dev/null
+++ b/usrp2/models/gpmc_model.v
@@ -0,0 +1,74 @@
+
+
+module gpmc_model
+ (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+ output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6,
+ output reg EM_NWE, output reg EM_NOE );
+
+ assign EM_CLK = 0;
+ reg [15:0] EM_D_int;
+ assign EM_D = EM_D_int;
+
+ initial
+ begin
+ EM_A <= 10'bz;
+ EM_NBE <= 2'b11;
+ EM_NWE <= 1;
+ EM_NOE <= 1;
+ EM_NCS4 <= 1;
+ EM_NCS6 <= 1;
+ EM_D_int <= 16'bz;
+ EM_WAIT0 <= 0; // FIXME this is actually an input
+ end
+
+ task GPMC_Write;
+ input [10:0] addr;
+ input [15:0] data;
+ begin
+ #2.3;
+ EM_A <= addr[10:1];
+ EM_D_int <= data;
+ #2.01;
+ EM_NCS6 <= 0;
+ #14;
+ EM_NWE <= 0;
+ #77.5;
+ EM_NCS6 <= 1;
+ //#1.5;
+ EM_NWE <= 1;
+ #6;
+ EM_A <= 10'bz;
+ EM_D_int <= 16'bz;
+ end
+ endtask // GPMC_Write
+
+ task GPMC_Read;
+ input [10:0] addr;
+ begin
+ #1.3;
+ EM_A <= addr[10:1];
+ #3;
+ EM_NCS6 <= 0;
+ #14;
+ EM_NOE <= 0;
+ #77.5;
+ EM_NCS6 <= 1;
+ //#1.5;
+ $display("Data Read from GPMC: %X",EM_D);
+ EM_NOE <= 1;
+ #254;
+ EM_A <= 10'bz;
+ end
+ endtask // GPMC_Read
+
+ initial
+ begin
+ #1000;
+ GPMC_Write(36,16'hBEEF);
+ #1000;
+ GPMC_Read(36);
+ #1000;
+ $finish;
+ end
+
+endmodule // gpmc_model
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 7bc4f6e5e..3f29f6d7f 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -43,8 +43,6 @@
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
- parameter Tp = 1;
-
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
@@ -71,13 +69,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
always @(posedge clk_in or posedge rst)
begin
if(rst)
- cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
+ cnt <= {`SPI_DIVIDER_LEN{1'b1}};
else
begin
if(!enable || cnt_zero)
- cnt <= #Tp divider;
+ cnt <= divider;
else
- cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+ cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
end
end
@@ -85,9 +83,9 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
always @(posedge clk_in or posedge rst)
begin
if(rst)
- clk_out <= #Tp 1'b0;
+ clk_out <= 1'b0;
else
- clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
+ clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
@@ -95,13 +93,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
begin
if(rst)
begin
- pos_edge <= #Tp 1'b0;
- neg_edge <= #Tp 1'b0;
+ pos_edge <= 1'b0;
+ neg_edge <= 1'b0;
end
else
begin
- pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
- neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
+ pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
+ neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..01de2584d 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -43,8 +43,8 @@
// low frequency of system clock this can be reduced.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
-//`define SPI_DIVIDER_LEN_8
-`define SPI_DIVIDER_LEN_16
+`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32
@@ -66,9 +66,9 @@
// Use SPI_MAX_CHAR for fine tuning the exact number, when using
// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
//
-`define SPI_MAX_CHAR_128
+//`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
-//`define SPI_MAX_CHAR_32
+`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_24
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index b17ac8b1f..c8c73706b 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -46,8 +46,6 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
- parameter Tp = 1;
-
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
@@ -92,13 +90,13 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
always @(posedge clk or posedge rst)
begin
if(rst)
- cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
+ cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
- cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
+ cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
- cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+ cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
@@ -106,132 +104,132 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
always @(posedge clk or posedge rst)
begin
if(rst)
- tip <= #Tp 1'b0;
+ tip <= 1'b0;
else if(go && ~tip)
- tip <= #Tp 1'b1;
+ tip <= 1'b1;
else if(tip && last && pos_edge)
- tip <= #Tp 1'b0;
+ tip <= 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
- s_out <= #Tp 1'b0;
+ s_out <= 1'b0;
else
- s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
+ s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
begin
if (rst)
- data <= #Tp {`SPI_MAX_CHAR{1'b0}};
+ data <= {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
- data[31:24] <= #Tp p_in[31:24];
+ data[31:24] <= p_in[31:24];
if (byte_sel[2])
- data[23:16] <= #Tp p_in[23:16];
+ data[23:16] <= p_in[23:16];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
- data[63:56] <= #Tp p_in[31:24];
+ data[63:56] <= p_in[31:24];
if (byte_sel[2])
- data[55:48] <= #Tp p_in[23:16];
+ data[55:48] <= p_in[23:16];
if (byte_sel[1])
- data[47:40] <= #Tp p_in[15:8];
+ data[47:40] <= p_in[15:8];
if (byte_sel[0])
- data[39:32] <= #Tp p_in[7:0];
+ data[39:32] <= p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
- data[95:88] <= #Tp p_in[31:24];
+ data[95:88] <= p_in[31:24];
if (byte_sel[2])
- data[87:80] <= #Tp p_in[23:16];
+ data[87:80] <= p_in[23:16];
if (byte_sel[1])
- data[79:72] <= #Tp p_in[15:8];
+ data[79:72] <= p_in[15:8];
if (byte_sel[0])
- data[71:64] <= #Tp p_in[7:0];
+ data[71:64] <= p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
- data[127:120] <= #Tp p_in[31:24];
+ data[127:120] <= p_in[31:24];
if (byte_sel[2])
- data[119:112] <= #Tp p_in[23:16];
+ data[119:112] <= p_in[23:16];
if (byte_sel[1])
- data[111:104] <= #Tp p_in[15:8];
+ data[111:104] <= p_in[15:8];
if (byte_sel[0])
- data[103:96] <= #Tp p_in[7:0];
+ data[103:96] <= p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
- data[31:24] <= #Tp p_in[31:24];
+ data[31:24] <= p_in[31:24];
if (byte_sel[2])
- data[23:16] <= #Tp p_in[23:16];
+ data[23:16] <= p_in[23:16];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
- data[63:56] <= #Tp p_in[31:24];
+ data[63:56] <= p_in[31:24];
if (byte_sel[2])
- data[55:48] <= #Tp p_in[23:16];
+ data[55:48] <= p_in[23:16];
if (byte_sel[1])
- data[47:40] <= #Tp p_in[15:8];
+ data[47:40] <= p_in[15:8];
if (byte_sel[0])
- data[39:32] <= #Tp p_in[7:0];
+ data[39:32] <= p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
- data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
+ data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
if (byte_sel[1])
- data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
+ data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[2])
- data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
+ data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[2])
- data[23:16] <= #Tp p_in[23:16];
+ data[23:16] <= p_in[23:16];
if (byte_sel[3])
- data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
+ data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
- data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+ data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 09b2e50e1..071aeefca 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_top.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -52,8 +52,6 @@ module spi_top
ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
);
- parameter Tp = 1;
-
// Wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
@@ -142,18 +140,18 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- wb_dat_o <= #Tp 32'b0;
+ wb_dat_o <= 32'b0;
else
- wb_dat_o <= #Tp wb_dat;
+ wb_dat_o <= wb_dat;
end
// Wb acknowledge
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- wb_ack_o <= #Tp 1'b0;
+ wb_ack_o <= 1'b0;
else
- wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
+ wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
// Wb error
@@ -163,47 +161,47 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- wb_int_o <= #Tp 1'b0;
+ wb_int_o <= 1'b0;
else if (ie && tip && last_bit && pos_edge)
- wb_int_o <= #Tp 1'b1;
+ wb_int_o <= 1'b1;
else if (wb_ack_o)
- wb_int_o <= #Tp 1'b0;
+ wb_int_o <= 1'b0;
end
// Divider register
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
+ divider <= {`SPI_DIVIDER_LEN{1'b0}};
else if (spi_divider_sel && wb_we_i && !tip)
begin
`ifdef SPI_DIVIDER_LEN_8
if (wb_sel_i[0])
- divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
+ divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0];
`endif
`ifdef SPI_DIVIDER_LEN_16
if (wb_sel_i[0])
- divider[7:0] <= #Tp wb_dat_i[7:0];
+ divider[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
+ divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8];
`endif
`ifdef SPI_DIVIDER_LEN_24
if (wb_sel_i[0])
- divider[7:0] <= #Tp wb_dat_i[7:0];
+ divider[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- divider[15:8] <= #Tp wb_dat_i[15:8];
+ divider[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
+ divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16];
`endif
`ifdef SPI_DIVIDER_LEN_32
if (wb_sel_i[0])
- divider[7:0] <= #Tp wb_dat_i[7:0];
+ divider[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- divider[15:8] <= #Tp wb_dat_i[15:8];
+ divider[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- divider[23:16] <= #Tp wb_dat_i[23:16];
+ divider[23:16] <= wb_dat_i[23:16];
if (wb_sel_i[3])
- divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
+ divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24];
`endif
end
end
@@ -212,16 +210,16 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
+ ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
else if(spi_ctrl_sel && wb_we_i && !tip)
begin
if (wb_sel_i[0])
- ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
+ ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
if (wb_sel_i[1])
- ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+ ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
end
else if(tip && last_bit && pos_edge)
- ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
+ ctrl[`SPI_CTRL_GO] <= 1'b0;
end
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
@@ -236,36 +234,36 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- ss <= #Tp {`SPI_SS_NB{1'b0}};
+ ss <= {`SPI_SS_NB{1'b0}};
else if(spi_ss_sel && wb_we_i && !tip)
begin
`ifdef SPI_SS_NB_8
if (wb_sel_i[0])
- ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
+ ss <= wb_dat_i[`SPI_SS_NB-1:0];
`endif
`ifdef SPI_SS_NB_16
if (wb_sel_i[0])
- ss[7:0] <= #Tp wb_dat_i[7:0];
+ ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
+ ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8];
`endif
`ifdef SPI_SS_NB_24
if (wb_sel_i[0])
- ss[7:0] <= #Tp wb_dat_i[7:0];
+ ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- ss[15:8] <= #Tp wb_dat_i[15:8];
+ ss[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
+ ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16];
`endif
`ifdef SPI_SS_NB_32
if (wb_sel_i[0])
- ss[7:0] <= #Tp wb_dat_i[7:0];
+ ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- ss[15:8] <= #Tp wb_dat_i[15:8];
+ ss[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- ss[23:16] <= #Tp wb_dat_i[23:16];
+ ss[23:16] <= wb_dat_i[23:16];
if (wb_sel_i[3])
- ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
+ ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24];
`endif
end
end
diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore
new file mode 100644
index 000000000..f8b57ea21
--- /dev/null
+++ b/usrp2/top/safe_u1e/.gitignore
@@ -0,0 +1,4 @@
+*~
+build
+*.log
+*.cmd
diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile
new file mode 100644
index 000000000..d28cc2b89
--- /dev/null
+++ b/usrp2/top/safe_u1e/Makefile
@@ -0,0 +1,246 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := safe_u1e
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/safe_u1e/safe_u1e.ucf \
+top/safe_u1e/safe_u1e.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf
new file mode 100644
index 000000000..cb6d6372e
--- /dev/null
+++ b/usrp2/top/safe_u1e/safe_u1e.ucf
@@ -0,0 +1,262 @@
+
+NET "CLK_FPGA_P" LOC = "Y11" ;
+NET "CLK_FPGA_N" LOC = "Y10" ;
+
+## GPMC
+NET "EM_CLK" LOC = "F11" ;
+
+NET "EM_D<15>" LOC = "D13" ;
+NET "EM_D<14>" LOC = "D15" ;
+NET "EM_D<13>" LOC = "C16" ;
+NET "EM_D<12>" LOC = "B20" ;
+NET "EM_D<11>" LOC = "A19" ;
+NET "EM_D<10>" LOC = "A17" ;
+NET "EM_D<9>" LOC = "E15" ;
+NET "EM_D<8>" LOC = "F15" ;
+NET "EM_D<7>" LOC = "E16" ;
+NET "EM_D<6>" LOC = "F16" ;
+NET "EM_D<5>" LOC = "B17" ;
+NET "EM_D<4>" LOC = "C17" ;
+NET "EM_D<3>" LOC = "B19" ;
+NET "EM_D<2>" LOC = "D19" ;
+NET "EM_D<1>" LOC = "C19" ;
+NET "EM_D<0>" LOC = "A20" ;
+
+NET "EM_A<10>" LOC = "C14" ;
+NET "EM_A<9>" LOC = "C10" ;
+NET "EM_A<8>" LOC = "C5" ;
+NET "EM_A<7>" LOC = "A18" ;
+NET "EM_A<6>" LOC = "A15" ;
+NET "EM_A<5>" LOC = "A12" ;
+NET "EM_A<4>" LOC = "A10" ;
+NET "EM_A<3>" LOC = "E7" ;
+NET "EM_A<2>" LOC = "A7" ;
+NET "EM_A<1>" LOC = "C15" ;
+
+#NET "EM_NCS6" LOC = "E17" ;
+#NET "EM_NCS5" LOC = "E10" ;
+NET "EM_NCS4" LOC = "E6" ;
+#NET "EM_NCS1" LOC = "D18" ;
+#NET "EM_NCS0" LOC = "D17" ;
+
+NET "EM_WAIT0" LOC = "F14" ;
+#NET "EM_NBE1" LOC = "D14" ;
+#NET "EM_NBE0" LOC = "A13" ;
+NET "EM_NWP" LOC = "F13" ;
+NET "EM_NWE" LOC = "B13" ;
+NET "EM_NOE" LOC = "A14" ;
+NET "EM_NADV_ALE" LOC = "B15" ;
+
+
+## Overo GPIO
+#NET "overo_gpio0" LOC = "F9" ;
+#NET "overo_gpio14" LOC = "C4" ;
+#NET "overo_gpio21" LOC = "D5" ;
+#NET "overo_gpio22" LOC = "A3" ;
+#NET "overo_gpio23" LOC = "B3" ;
+#NET "overo_gpio64" LOC = "A4" ;
+#NET "overo_gpio65" LOC = "F8" ;
+#NET "overo_gpio127" LOC = "C8" ;
+#NET "overo_gpio128" LOC = "G8" ;
+#NET "overo_gpio144" LOC = "A5" ;
+#NET "overo_gpio145" LOC = "C7" ;
+#NET "overo_gpio146" LOC = "A6" ;
+#NET "overo_gpio147" LOC = "B6" ;
+#NET "overo_gpio163" LOC = "D7" ;
+#NET "overo_gpio170" LOC = "E8" ;
+#NET "overo_gpio176" LOC = "B4" ;
+
+## Overo UART
+#NET "overo_txd1" LOC = "C6" ;
+#NET "overo_rxd1" LOC = "D6" ;
+
+#NET "FPGA_TXD" LOC = "U1" ;
+#NET "FPGA_RXD" LOC = "T6" ;
+
+#NET "SYSEN" LOC = "C11" ;
+
+#NET "db_scl" LOC = "U4" ;
+#NET "db_sda" LOC = "U5" ;
+#NET "db_sclk_rx" LOC = "W3" ;
+#NET "db_miso_rx" LOC = "W2" ;
+#NET "db_mosi_rx" LOC = "V4" ;
+#NET "db_sen_rx" LOC = "V3" ;
+#NET "db_sclk_tx" LOC = "Y1" ;
+#NET "db_miso_tx" LOC = "W1" ;
+#NET "db_mosi_tx" LOC = "R3" ;
+#NET "db_sen_tx" LOC = "T4" ;
+
+## Clock Gen
+#NET "cgen_miso" LOC = "U2" ;
+#NET "cgen_mosi" LOC = "V1" ;
+#NET "cgen_sclk" LOC = "R5" ;
+#NET "cgen_sen_b" LOC = "T1" ;
+#NET "cgen_st_status" LOC = "D4" ;
+#NET "cgen_st_ld" LOC = "D1" ;
+#NET "cgen_st_refmon" LOC = "E1" ;
+#NET "cgen_sync_b" LOC = "M1" ;
+#NET "cgen_ref_sel" LOC = "J1" ;
+
+## Debug pins
+NET "debug_led<2>" LOC = "T5" ;
+NET "debug_led<1>" LOC = "R2" ;
+NET "debug_led<0>" LOC = "R1" ;
+NET "debug<0>" LOC = "P6" ;
+NET "debug<1>" LOC = "R6" ;
+NET "debug<2>" LOC = "P1" ;
+NET "debug<3>" LOC = "P2" ;
+NET "debug<4>" LOC = "N6" ;
+NET "debug<5>" LOC = "N5" ;
+NET "debug<6>" LOC = "N1" ;
+NET "debug<7>" LOC = "K2" ;
+NET "debug<8>" LOC = "K3" ;
+NET "debug<9>" LOC = "K6" ;
+NET "debug<10>" LOC = "L5" ;
+NET "debug<11>" LOC = "H2" ;
+NET "debug<12>" LOC = "K4" ;
+NET "debug<13>" LOC = "K5" ;
+NET "debug<14>" LOC = "G1" ;
+NET "debug<15>" LOC = "H1" ;
+NET "debug<16>" LOC = "H5" ;
+NET "debug<17>" LOC = "H6" ;
+NET "debug<18>" LOC = "E3" ;
+NET "debug<19>" LOC = "E4" ;
+NET "debug<20>" LOC = "G5" ;
+NET "debug<21>" LOC = "G6" ;
+NET "debug<22>" LOC = "F2" ;
+NET "debug<23>" LOC = "F1" ;
+NET "debug<24>" LOC = "H3" ;
+NET "debug<25>" LOC = "H4" ;
+NET "debug<26>" LOC = "F4" ;
+NET "debug<27>" LOC = "F5" ;
+NET "debug<28>" LOC = "C2" ;
+NET "debug<29>" LOC = "C1" ;
+NET "debug<30>" LOC = "F3" ;
+NET "debug<31>" LOC = "G3" ;
+NET "debug_clk<0>" LOC = "L6" ;
+NET "debug_clk<1>" LOC = "M5" ;
+
+#NET "debug_pb<2>" LOC = "Y2" ;
+#NET "debug_pb<1>" LOC = "AA1" ;
+#NET "debug_pb<0>" LOC = "N3" ;
+
+#NET "dip_sw<7>" LOC = "T3" ;
+#NET "dip_sw<6>" LOC = "U3" ;
+#NET "dip_sw<5>" LOC = "M3" ;
+#NET "dip_sw<4>" LOC = "N4" ;
+#NET "dip_sw<3>" LOC = "J3" ;
+#NET "dip_sw<2>" LOC = "J4" ;
+#NET "dip_sw<1>" LOC = "J6" ;
+#NET "dip_sw<0>" LOC = "J7" ;
+
+## AD9862 Interface
+#NET "aux_sdi_codec" LOC = "F19" ;
+#NET "aux_sdo_codec" LOC = "F18" ;
+#NET "aux_sclk_codec" LOC = "D21" ;
+#NET "reset_codec" LOC = "D22" ;
+#NET "sen_codec" LOC = "D20" ;
+#NET "mosi_codec" LOC = "E19" ;
+#NET "miso_codec" LOC = "F21" ;
+#NET "sclk_codec" LOC = "E20" ;
+
+#NET "RXSYNC" LOC = "F22" ;
+
+#NET "DB<11>" LOC = "E22" ;
+#NET "DB<10>" LOC = "J19" ;
+#NET "DB<9>" LOC = "H20" ;
+#NET "DB<8>" LOC = "G19" ;
+#NET "DB<7>" LOC = "F20" ;
+#NET "DB<6>" LOC = "K16" ;
+#NET "DB<5>" LOC = "J17" ;
+#NET "DB<4>" LOC = "H22" ;
+#NET "DB<3>" LOC = "G22" ;
+#NET "DB<2>" LOC = "H17" ;
+#NET "DB<1>" LOC = "H18" ;
+#NET "DB<0>" LOC = "K20" ;
+#NET "DA<11>" LOC = "J20" ;
+#NET "DA<10>" LOC = "K19" ;
+#NET "DA<9>" LOC = "K18" ;
+#NET "DA<8>" LOC = "L22" ;
+#NET "DA<7>" LOC = "K22" ;
+#NET "DA<6>" LOC = "N22" ;
+#NET "DA<5>" LOC = "M22" ;
+#NET "DA<4>" LOC = "N20" ;
+#NET "DA<3>" LOC = "N19" ;
+#NET "DA<2>" LOC = "R22" ;
+#NET "DA<1>" LOC = "P22" ;
+#NET "DA<0>" LOC = "N17" ;
+
+#NET "TX<13>" LOC = "P19" ;
+#NET "TX<12>" LOC = "R18" ;
+#NET "TX<11>" LOC = "U20" ;
+#NET "TX<10>" LOC = "T20" ;
+#NET "TX<9>" LOC = "R19" ;
+#NET "TX<8>" LOC = "R20" ;
+#NET "TX<7>" LOC = "W22" ;
+#NET "TX<6>" LOC = "Y22" ;
+#NET "TX<5>" LOC = "T18" ;
+#NET "TX<4>" LOC = "T17" ;
+#NET "TX<3>" LOC = "W19" ;
+#NET "TX<2>" LOC = "V20" ;
+#NET "TX<1>" LOC = "Y21" ;
+#NET "TX<0>" LOC = "AA22" ;
+#NET "TXSYNC" LOC = "U18" ;
+#NET "TXBLANK" LOC = "U19" ;
+
+#NET "PPS_IN" LOC = "M17" ;
+
+#NET "io_tx<0>" LOC = "AB20" ;
+#NET "io_tx<1>" LOC = "Y17" ;
+#NET "io_tx<2>" LOC = "Y16" ;
+#NET "io_tx<3>" LOC = "U16" ;
+#NET "io_tx<4>" LOC = "V16" ;
+#NET "io_tx<5>" LOC = "AB19" ;
+#NET "io_tx<6>" LOC = "AA19" ;
+#NET "io_tx<7>" LOC = "U14" ;
+#NET "io_tx<8>" LOC = "U15" ;
+#NET "io_tx<9>" LOC = "AB17" ;
+#NET "io_tx<10>" LOC = "AB18" ;
+#NET "io_tx<11>" LOC = "Y13" ;
+#NET "io_tx<12>" LOC = "W14" ;
+#NET "io_tx<13>" LOC = "U13" ;
+#NET "io_tx<14>" LOC = "AA15" ;
+#NET "io_tx<15>" LOC = "AB14" ;
+
+#NET "io_rx<0>" LOC = "Y8" ;
+#NET "io_rx<1>" LOC = "Y9" ;
+#NET "io_rx<2>" LOC = "V7" ;
+#NET "io_rx<3>" LOC = "U8" ;
+#NET "io_rx<4>" LOC = "V10" ;
+#NET "io_rx<5>" LOC = "U9" ;
+#NET "io_rx<6>" LOC = "AB7" ;
+#NET "io_rx<7>" LOC = "AA8" ;
+#NET "io_rx<8>" LOC = "W8" ;
+#NET "io_rx<9>" LOC = "V8" ;
+#NET "io_rx<10>" LOC = "AB5" ;
+#NET "io_rx<11>" LOC = "AB6" ;
+#NET "io_rx<12>" LOC = "AB4" ;
+#NET "io_rx<13>" LOC = "AA4" ;
+#NET "io_rx<14>" LOC = "W5" ;
+#NET "io_rx<15>" LOC = "Y4" ;
+
+#NET "CLKOUT2_CODEC" LOC = "U12" ;
+#NET "CLKOUT1_CODEC" LOC = "V12" ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "AB21" ;
+#NET "fpga_cfg_din" LOC = "W17" ;
+#NET "fpga_cfg_cclk" LOC = "V17" ;
+#NET "fpga_cfg_init_b" LOC = "W15" ;
+
+## Unnamed, need to figure out what they do
+#NET "unnamed_net37" LOC = "B1" ;
+#NET "unnamed_net36" LOC = "B22" ;
+#NET "unnamed_net35" LOC = "D2" ;
+#NET "unnamed_net34" LOC = "A21" ;
+#NET "unnamed_net45" LOC = "F7" ;
+#NET "unnamed_net44" LOC = "V6" ;
+#NET "unnamed_net43" LOC = "AA3" ;
+#NET "unnamed_net42" LOC = "AB3" ;
+
+#NET "GND" LOC = "V19" ;
diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v
new file mode 100644
index 000000000..dee9c6067
--- /dev/null
+++ b/usrp2/top/safe_u1e/safe_u1e.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module safe_u1e
+ (
+ input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+
+ // GPMC
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A,
+ input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE
+ );
+
+ // FPGA-specific pins connections
+ wire clk_fpga;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
+ clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+ // Debug circuitry
+ reg [31:0] ctr;
+ always @(posedge clk_fpga)
+ ctr <= ctr + 1;
+
+
+ assign debug_led = ctr[27:25];
+ assign debug_clk = { EM_CLK, clk_fpga };
+ assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ { EM_D } };
+
+ wire EM_output_enable = (~EM_NOE & ~EM_NCS4);
+ wire [15:0] EM_D_out;
+
+ assign EM_D = EM_output_enable ? EM_D_out : 16'bz;
+
+ ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
+ (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out),
+ .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
+
+
+endmodule // safe_u2plus
diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/usrp2/top/u1e/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
new file mode 100644
index 000000000..306ab5bae
--- /dev/null
+++ b/usrp2/top/u1e/Makefile
@@ -0,0 +1,248 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u1e
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio16LE.v \
+control_lib/ram_2port.v \
+control_lib/ram_2port_mixed_width.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus_16LE.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+gpmc/gpmc.v \
+top/u1e/u1e_core.v \
+top/u1e/u1e.ucf \
+top/u1e/u1e.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..291c723b8
--- /dev/null
+++ b/usrp2/top/u1e/cmdfile
@@ -0,0 +1,20 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+
diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:
+ iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+ rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..319645af6
--- /dev/null
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,36 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+
+ wire [2:0] debug_led;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ xlnx_glbl glbl (.GSR(),.GTS());
+
+ initial begin
+ $dumpfile("tb_u1e.lxt");
+ $dumpvars(0,tb_u1e);
+ end
+
+ // GPMC
+ wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+ wire [15:0] EM_D;
+ wire [10:1] EM_A;
+ wire [1:0] EM_NBE;
+
+ reg clk_fpga = 0;
+ always #15.625 clk_fpga = ~clk_fpga;
+
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+ gpmc_model gpmc_model
+ (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+endmodule // tb_u1e
diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
new file mode 100644
index 000000000..f237eb60c
--- /dev/null
+++ b/usrp2/top/u1e/u1e.ucf
@@ -0,0 +1,260 @@
+
+NET "CLK_FPGA_P" LOC = "Y11" ;
+NET "CLK_FPGA_N" LOC = "Y10" ;
+
+## GPMC
+NET "EM_D<15>" LOC = "D13" ;
+NET "EM_D<14>" LOC = "D15" ;
+NET "EM_D<13>" LOC = "C16" ;
+NET "EM_D<12>" LOC = "B20" ;
+NET "EM_D<11>" LOC = "A19" ;
+NET "EM_D<10>" LOC = "A17" ;
+NET "EM_D<9>" LOC = "E15" ;
+NET "EM_D<8>" LOC = "F15" ;
+NET "EM_D<7>" LOC = "E16" ;
+NET "EM_D<6>" LOC = "F16" ;
+NET "EM_D<5>" LOC = "B17" ;
+NET "EM_D<4>" LOC = "C17" ;
+NET "EM_D<3>" LOC = "B19" ;
+NET "EM_D<2>" LOC = "D19" ;
+NET "EM_D<1>" LOC = "C19" ;
+NET "EM_D<0>" LOC = "A20" ;
+
+NET "EM_A<10>" LOC = "C14" ;
+NET "EM_A<9>" LOC = "C10" ;
+NET "EM_A<8>" LOC = "C5" ;
+NET "EM_A<7>" LOC = "A18" ;
+NET "EM_A<6>" LOC = "A15" ;
+NET "EM_A<5>" LOC = "A12" ;
+NET "EM_A<4>" LOC = "A10" ;
+NET "EM_A<3>" LOC = "E7" ;
+NET "EM_A<2>" LOC = "A7" ;
+NET "EM_A<1>" LOC = "C15" ;
+
+NET "EM_NCS6" LOC = "E17" ;
+#NET "EM_NCS5" LOC = "E10" ;
+NET "EM_NCS4" LOC = "E6" ;
+#NET "EM_NCS1" LOC = "D18" ;
+#NET "EM_NCS0" LOC = "D17" ;
+
+NET "EM_CLK" LOC = "F11" ;
+NET "EM_WAIT0" LOC = "F14" ;
+NET "EM_NBE<1>" LOC = "D14" ;
+NET "EM_NBE<0>" LOC = "A13" ;
+NET "EM_NWE" LOC = "B13" ;
+NET "EM_NOE" LOC = "A14" ;
+#NET "EM_NADV_ALE" LOC = "B15" ;
+#NET "EM_NWP" LOC = "F13" ;
+
+## Overo GPIO
+#NET "overo_gpio0" LOC = "F9" ;
+#NET "overo_gpio14" LOC = "C4" ;
+#NET "overo_gpio21" LOC = "D5" ;
+#NET "overo_gpio22" LOC = "A3" ;
+#NET "overo_gpio23" LOC = "B3" ;
+#NET "overo_gpio64" LOC = "A4" ;
+#NET "overo_gpio65" LOC = "F8" ;
+#NET "overo_gpio127" LOC = "C8" ;
+#NET "overo_gpio128" LOC = "G8" ;
+NET "overo_gpio144" LOC = "A5" ; # tx_have_space
+NET "overo_gpio145" LOC = "C7" ; # tx_underrun
+NET "overo_gpio146" LOC = "A6" ; # rx_have_data
+NET "overo_gpio147" LOC = "B6" ; # rx_overrun
+#NET "overo_gpio163" LOC = "D7" ;
+#NET "overo_gpio170" LOC = "E8" ;
+#NET "overo_gpio176" LOC = "B4" ;
+
+## Overo UART
+#NET "overo_txd1" LOC = "C6" ;
+#NET "overo_rxd1" LOC = "D6" ;
+
+NET "FPGA_TXD" LOC = "U1" ;
+NET "FPGA_RXD" LOC = "T6" ;
+
+#NET "SYSEN" LOC = "C11" ;
+
+NET "db_scl" LOC = "U4" ;
+NET "db_sda" LOC = "U5" ;
+#NET "db_sclk_rx" LOC = "W3" ;
+#NET "db_miso_rx" LOC = "W2" ;
+#NET "db_mosi_rx" LOC = "V4" ;
+#NET "db_sen_rx" LOC = "V3" ;
+#NET "db_sclk_tx" LOC = "Y1" ;
+#NET "db_miso_tx" LOC = "W1" ;
+#NET "db_mosi_tx" LOC = "R3" ;
+#NET "db_sen_tx" LOC = "T4" ;
+
+## Clock Gen
+#NET "cgen_miso" LOC = "U2" ;
+#NET "cgen_mosi" LOC = "V1" ;
+#NET "cgen_sclk" LOC = "R5" ;
+#NET "cgen_sen_b" LOC = "T1" ;
+#NET "cgen_st_status" LOC = "D4" ;
+#NET "cgen_st_ld" LOC = "D1" ;
+#NET "cgen_st_refmon" LOC = "E1" ;
+#NET "cgen_sync_b" LOC = "M1" ;
+#NET "cgen_ref_sel" LOC = "J1" ;
+
+## Debug pins
+NET "debug_led<2>" LOC = "T5" ;
+NET "debug_led<1>" LOC = "R2" ;
+NET "debug_led<0>" LOC = "R1" ;
+NET "debug<0>" LOC = "P6" ;
+NET "debug<1>" LOC = "R6" ;
+NET "debug<2>" LOC = "P1" ;
+NET "debug<3>" LOC = "P2" ;
+NET "debug<4>" LOC = "N6" ;
+NET "debug<5>" LOC = "N5" ;
+NET "debug<6>" LOC = "N1" ;
+NET "debug<7>" LOC = "K2" ;
+NET "debug<8>" LOC = "K3" ;
+NET "debug<9>" LOC = "K6" ;
+NET "debug<10>" LOC = "L5" ;
+NET "debug<11>" LOC = "H2" ;
+NET "debug<12>" LOC = "K4" ;
+NET "debug<13>" LOC = "K5" ;
+NET "debug<14>" LOC = "G1" ;
+NET "debug<15>" LOC = "H1" ;
+NET "debug<16>" LOC = "H5" ;
+NET "debug<17>" LOC = "H6" ;
+NET "debug<18>" LOC = "E3" ;
+NET "debug<19>" LOC = "E4" ;
+NET "debug<20>" LOC = "G5" ;
+NET "debug<21>" LOC = "G6" ;
+NET "debug<22>" LOC = "F2" ;
+NET "debug<23>" LOC = "F1" ;
+NET "debug<24>" LOC = "H3" ;
+NET "debug<25>" LOC = "H4" ;
+NET "debug<26>" LOC = "F4" ;
+NET "debug<27>" LOC = "F5" ;
+NET "debug<28>" LOC = "C2" ;
+NET "debug<29>" LOC = "C1" ;
+NET "debug<30>" LOC = "F3" ;
+NET "debug<31>" LOC = "G3" ;
+NET "debug_clk<0>" LOC = "L6" ;
+NET "debug_clk<1>" LOC = "M5" ;
+
+NET "debug_pb<2>" LOC = "Y2" ;
+NET "debug_pb<1>" LOC = "AA1" ;
+NET "debug_pb<0>" LOC = "N3" ;
+
+NET "dip_sw<7>" LOC = "T3" ;
+NET "dip_sw<6>" LOC = "U3" ;
+NET "dip_sw<5>" LOC = "M3" ;
+NET "dip_sw<4>" LOC = "N4" ;
+NET "dip_sw<3>" LOC = "J3" ;
+NET "dip_sw<2>" LOC = "J4" ;
+NET "dip_sw<1>" LOC = "J6" ;
+NET "dip_sw<0>" LOC = "J7" ;
+
+## AD9862 Interface
+#NET "aux_sdi_codec" LOC = "F19" ;
+#NET "aux_sdo_codec" LOC = "F18" ;
+#NET "aux_sclk_codec" LOC = "D21" ;
+#NET "reset_codec" LOC = "D22" ;
+#NET "sen_codec" LOC = "D20" ;
+#NET "mosi_codec" LOC = "E19" ;
+#NET "miso_codec" LOC = "F21" ;
+#NET "sclk_codec" LOC = "E20" ;
+
+#NET "RXSYNC" LOC = "F22" ;
+
+#NET "DB<11>" LOC = "E22" ;
+#NET "DB<10>" LOC = "J19" ;
+#NET "DB<9>" LOC = "H20" ;
+#NET "DB<8>" LOC = "G19" ;
+#NET "DB<7>" LOC = "F20" ;
+#NET "DB<6>" LOC = "K16" ;
+#NET "DB<5>" LOC = "J17" ;
+#NET "DB<4>" LOC = "H22" ;
+#NET "DB<3>" LOC = "G22" ;
+#NET "DB<2>" LOC = "H17" ;
+#NET "DB<1>" LOC = "H18" ;
+#NET "DB<0>" LOC = "K20" ;
+#NET "DA<11>" LOC = "J20" ;
+#NET "DA<10>" LOC = "K19" ;
+#NET "DA<9>" LOC = "K18" ;
+#NET "DA<8>" LOC = "L22" ;
+#NET "DA<7>" LOC = "K22" ;
+#NET "DA<6>" LOC = "N22" ;
+#NET "DA<5>" LOC = "M22" ;
+#NET "DA<4>" LOC = "N20" ;
+#NET "DA<3>" LOC = "N19" ;
+#NET "DA<2>" LOC = "R22" ;
+#NET "DA<1>" LOC = "P22" ;
+#NET "DA<0>" LOC = "N17" ;
+
+#NET "TX<13>" LOC = "P19" ;
+#NET "TX<12>" LOC = "R18" ;
+#NET "TX<11>" LOC = "U20" ;
+#NET "TX<10>" LOC = "T20" ;
+#NET "TX<9>" LOC = "R19" ;
+#NET "TX<8>" LOC = "R20" ;
+#NET "TX<7>" LOC = "W22" ;
+#NET "TX<6>" LOC = "Y22" ;
+#NET "TX<5>" LOC = "T18" ;
+#NET "TX<4>" LOC = "T17" ;
+#NET "TX<3>" LOC = "W19" ;
+#NET "TX<2>" LOC = "V20" ;
+#NET "TX<1>" LOC = "Y21" ;
+#NET "TX<0>" LOC = "AA22" ;
+#NET "TXSYNC" LOC = "U18" ;
+#NET "TXBLANK" LOC = "U19" ;
+
+#NET "PPS_IN" LOC = "M17" ;
+
+NET "io_tx<0>" LOC = "AB20" ;
+NET "io_tx<1>" LOC = "Y17" ;
+NET "io_tx<2>" LOC = "Y16" ;
+NET "io_tx<3>" LOC = "U16" ;
+NET "io_tx<4>" LOC = "V16" ;
+NET "io_tx<5>" LOC = "AB19" ;
+NET "io_tx<6>" LOC = "AA19" ;
+NET "io_tx<7>" LOC = "U14" ;
+NET "io_tx<8>" LOC = "U15" ;
+NET "io_tx<9>" LOC = "AB17" ;
+NET "io_tx<10>" LOC = "AB18" ;
+NET "io_tx<11>" LOC = "Y13" ;
+NET "io_tx<12>" LOC = "W14" ;
+NET "io_tx<13>" LOC = "U13" ;
+NET "io_tx<14>" LOC = "AA15" ;
+NET "io_tx<15>" LOC = "AB14" ;
+
+NET "io_rx<0>" LOC = "Y8" ;
+NET "io_rx<1>" LOC = "Y9" ;
+NET "io_rx<2>" LOC = "V7" ;
+NET "io_rx<3>" LOC = "U8" ;
+NET "io_rx<4>" LOC = "V10" ;
+NET "io_rx<5>" LOC = "U9" ;
+NET "io_rx<6>" LOC = "AB7" ;
+NET "io_rx<7>" LOC = "AA8" ;
+NET "io_rx<8>" LOC = "W8" ;
+NET "io_rx<9>" LOC = "V8" ;
+NET "io_rx<10>" LOC = "AB5" ;
+NET "io_rx<11>" LOC = "AB6" ;
+NET "io_rx<12>" LOC = "AB4" ;
+NET "io_rx<13>" LOC = "AA4" ;
+NET "io_rx<14>" LOC = "W5" ;
+NET "io_rx<15>" LOC = "Y4" ;
+
+#NET "CLKOUT2_CODEC" LOC = "U12" ;
+#NET "CLKOUT1_CODEC" LOC = "V12" ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "AB21" ;
+#NET "fpga_cfg_din" LOC = "W17" ;
+#NET "fpga_cfg_cclk" LOC = "V17" ;
+#NET "fpga_cfg_init_b" LOC = "W15" ;
+
+## Unnamed, need to figure out what they do
+#NET "unnamed_net37" LOC = "B1" ;
+#NET "unnamed_net36" LOC = "B22" ;
+#NET "unnamed_net35" LOC = "D2" ;
+#NET "unnamed_net34" LOC = "A21" ;
+#NET "unnamed_net45" LOC = "F7" ;
+#NET "unnamed_net44" LOC = "V6" ;
+#NET "unnamed_net43" LOC = "AA3" ;
+#NET "unnamed_net42" LOC = "AB3" ;
+
+#NET "GND" LOC = "V19" ;
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
new file mode 100644
index 000000000..667372434
--- /dev/null
+++ b/usrp2/top/u1e/u1e.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+ input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD,
+
+ // GPMC
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+
+ inout db_sda, inout db_scl, // I2C
+ output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls
+ inout [15:0] io_tx, inout [15:0] io_rx
+ );
+
+ // FPGA-specific pins connections
+ wire clk_fpga;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
+ clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+ .db_sda(db_sda), .db_scl(db_scl),
+ .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
+ .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
+ .io_tx(io_tx), .io_rx(io_rx) );
+
+endmodule // u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
new file mode 100644
index 000000000..12c566b6c
--- /dev/null
+++ b/usrp2/top/u1e/u1e_core.v
@@ -0,0 +1,214 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e_core
+ (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+ input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd,
+
+ // GPMC
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+
+ inout db_sda, inout db_scl,
+ output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
+ inout [15:0] io_tx, inout [15:0] io_rx
+ );
+
+ wire wb_clk, wb_rst;
+
+ // /////////////////////////////////////////////////////////////////////////////////////
+ // GPMC Slave to Wishbone Master
+ localparam dw = 16;
+ localparam aw = 11;
+ localparam sw = 2;
+
+ wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
+ wire [aw-1:0] m0_adr;
+ wire [sw-1:0] m0_sel;
+ wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
+
+ gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
+ .EM_NOE(EM_NOE),
+
+ .wb_clk(wb_clk), .wb_rst(wb_rst),
+ .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
+ .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
+ .wb_ack_i(m0_ack));
+
+ assign wb_clk = clk_fpga;
+
+ // /////////////////////////////////////////////////////////////////////////////////////
+ // Wishbone Intercon, single master
+ wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
+ s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
+ s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
+ sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
+ wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+ wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+ wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
+ wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+ wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
+ wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+ wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
+ wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+ wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
+ wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+ wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
+ wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
+
+ wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
+ .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF),
+ .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF),
+ .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF),
+ .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF),
+ .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF),
+ .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF),
+ .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF),
+ .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF))
+ wb_1master
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
+ .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+ .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+ .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+ .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+ .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+ .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+ .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+ .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+ .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+ .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+ .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+ .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+ .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+ .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+ .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+ .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+ .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+ .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+ .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+ .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+ .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+ .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+ .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+ .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+ .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+ .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+ .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+ .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+ .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+ .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+ .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+ .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+ .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
+
+ assign s6_ack = 0; assign s7_ack = 0;
+ assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0;
+ assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0;
+
+ // /////////////////////////////////////////////////////////////////////////////////////
+ // Slave 0, LEDs and Switches
+
+ reg [15:0] reg_fast, reg_slow;
+ localparam REG_FAST = 7'd4;
+ localparam REG_SWITCHES = 7'd6;
+ localparam REG_GPIOS = 7'd8;
+
+ reg [3:0] reg_gpios;
+
+ always @(posedge wb_clk)
+ if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST))
+ reg_fast <= s0_dat_mosi;
+
+ always @(posedge wb_clk)
+ if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS))
+ reg_gpios <= s0_dat_mosi;
+
+ assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast :
+ (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} :
+ 16'hBEEF;
+ assign s0_ack = s0_stb & s0_cyc;
+
+ assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios;
+
+ // /////////////////////////////////////////////////////////////////////////////////////
+ // Slave 1, UART
+ // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock
+
+ simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack),
+ .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso),
+ .rx_int_o(),.tx_int_o(),
+ .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o());
+
+ // /////////////////////////////////////////////////////////////////////////////////////
+ // Slave 2, SPI
+
+ /*
+ spi_top shared_spi
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+ .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+ .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
+ .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+ */
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Slave 3, I2C
+
+ wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
+ i2c_master_top #(.ARST_LVL(1)) i2c
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
+ .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
+ .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+ .wb_ack_o(s3_ack),.wb_inta_o(),
+ .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+ .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+ assign s3_dat_miso[15:8] = 8'd0;
+
+ // I2C -- Don't use external transistors for open drain, the FPGA implements this
+ IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // GPIOs -- Slave #4
+
+ wire [31:0] atr_lines;
+ wire [31:0] debug_gpio_0, debug_gpio_1;
+
+ nsgpio16LE
+ nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+ .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
+ .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+ .gpio( {io_tx,io_rx} ) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Settings Bus -- Slave #5
+
+ wire [7:0] set_addr;
+ wire [31:0] set_data;
+ wire set_stb;
+
+ settings_bus_16LE settings_bus_16LE
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi),
+ .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack),
+ .strobe(set_stb),.addr(set_addr),.data(set_data) );
+
+ // /////////////////////////////////////////////////////////////////////////////////////
+ // Debug Pins
+
+ // Debug circuitry
+ assign debug_clk = { EM_CLK, clk_fpga };
+ assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ { EM_D } };
+
+ assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] };
+ assign debug_gpio_1 = { debug_txd, debug_rxd };
+
+ assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board
+
+endmodule // u1e_core
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