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-rw-r--r--usrp2/top/safe_u1plus/safe_u1plus.ucf11
-rw-r--r--usrp2/top/safe_u1plus/safe_u1plus.v5
2 files changed, 10 insertions, 6 deletions
diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf
index 1a078a9cc..a0c743525 100644
--- a/usrp2/top/safe_u1plus/safe_u1plus.ucf
+++ b/usrp2/top/safe_u1plus/safe_u1plus.ucf
@@ -5,6 +5,12 @@ NET "reset_n" LOC = "D5" ;
NET "CLK_FPGA_P" LOC = "R7" ;
NET "CLK_FPGA_N" LOC = "T7" ;
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "T15" ;
+#NET "fpga_cfg_din" LOC = "T14" ;
+#NET "fpga_cfg_cclk" LOC = "R14" ;
+NET "fpga_cfg_init_b" LOC = "T12" ;
+
#NET "TMS" LOC = "B2" ;
#NET "TDO" LOC = "B16" ;
@@ -22,13 +28,8 @@ NET "CLK_FPGA_N" LOC = "T7" ;
#NET "GPIF_CTL2" LOC = "M11" ;
#NET "GPIF_CTL1" LOC = "M9" ;
#NET "GPIF_CTL0" LOC = "M7" ;
-#NET "fpga_cfg_prog_b" LOC = "A2" ;
-#NET "fpga_cfg_done" LOC = "T15" ;
-#NET "fpga_cfg_din" LOC = "T14" ;
-#NET "fpga_cfg_cclk" LOC = "R14" ;
#NET "SDA_FPGA" LOC = "T13" ;
#NET "SCL_FPGA" LOC = "R13" ;
-#NET "fpga_cfg_init_b" LOC = "T12" ;
#NET "FX2_PA7_FLAGD" LOC = "P12" ;
#NET "mystery_bus_2" LOC = "T11" ;
#NET "FX2_PA6_PKTEND" LOC = "R11" ;
diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v
index 108364833..e55c7f0be 100644
--- a/usrp2/top/safe_u1plus/safe_u1plus.v
+++ b/usrp2/top/safe_u1plus/safe_u1plus.v
@@ -4,8 +4,11 @@
module safe_u1plus
(input CLK_FPGA_P, input CLK_FPGA_N,
input reset_n,
- output [2:0] debug_led // LED4 is shared w/INIT_B
+ output [2:0] debug_led, // LED4 is shared w/INIT_B
+ output fpga_cfg_init_b
);
+
+ assign fpga_cfg_init_b = 1;
// FPGA-specific pins connections
wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;