2 files changed, 6 insertions, 16 deletions
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index ae6cdbdf3..f17c2816f 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -102,8 +102,8 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
-   round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
    reg 	       strobe_cic_d1;
    always @(posedge clk) strobe_cic_d1 <= strobe_cic;
    
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 52f8cd5be..97923b9bf 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -32,7 +32,8 @@ module rx_dcoffset
 
    localparam int_width = WIDTH + alpha_shift;
    reg [int_width-1:0] integrator;
-   
+   wire [WIDTH-1:0]    quantized;
+
    always @(posedge clk)
      if(rst)
        begin
@@ -47,19 +48,8 @@ module rx_dcoffset
      else if(~fixed)
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
-   wire [WIDTH-1:0] quantized;
-   wire [int_width-WIDTH:0] q_err;
-   wire [int_width-1:0]     q_err_ext;
-   wire [int_width-1:0]     q_loop;
-
-   round #(.bits_in(int_width), .bits_out(WIDTH)) quantizer
-     (.in(q_loop), .out(quantized), .err(q_err));
-   
-   sign_extend #(.bits_in(int_width-WIDTH+1),.bits_out(int_width)) sign_extend
-     (.in(q_err), .out(q_err_ext));
-   
-   add2_and_clip_reg #(.WIDTH(int_width)) sd_fixed
-     (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
+   round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
+     (.clk(clk), .reset(rst), .in(integrator), .out(quantized));
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
      (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));