diff options
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/sdr_lib/Makefile.srcs | 1 | ||||
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx.v | 21 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_frontend.v | 16 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 4 |
4 files changed, 22 insertions, 20 deletions
diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs index 90eede20f..4a85726a9 100644 --- a/usrp2/sdr_lib/Makefile.srcs +++ b/usrp2/sdr_lib/Makefile.srcs @@ -30,6 +30,7 @@ round.v \ round_reg.v \ rx_control.v \ rx_dcoffset.v \ +rx_frontend.v \ sign_extend.v \ small_hb_dec.v \ small_hb_int.v \ diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 36d56174e..ae6cdbdf3 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -21,8 +21,8 @@ module dsp_core_rx (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [17:0] adc_i, input adc_ovf_a, - input [17:0] adc_q, input adc_ovf_b, + input [17:0] adc_i, input adc_ovf_i, + input [17:0] adc_q, input adc_ovf_q, output [31:0] sample, input run, @@ -31,7 +31,6 @@ module dsp_core_rx ); wire [15:0] scale_i, scale_q; - reg [13:0] adc_i, adc_q; wire [31:0] phase_inc; reg [31:0] phase; @@ -69,7 +68,7 @@ module dsp_core_rx MULT18X18S mult_i (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .A(adc_i), // 18-bit multiplier input .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input .C(clk), // Clock input .CE(1), // Clock enable input @@ -78,7 +77,7 @@ module dsp_core_rx MULT18X18S mult_q (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .A(adc_q), // 18-bit multiplier input .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input .C(clk), // Clock input .CE(1), // Clock enable input @@ -125,11 +124,13 @@ module dsp_core_rx (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); - round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); - - assign sample = sample_reg; - assign strobe = strobe_hb2; + round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out)); + round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out)); + reg strobe_out; + always @(posedge clk) strobe_out <= strobe_hb2; + + assign sample = {i_hb2,q_hb2}; + assign strobe = strobe_out; assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; endmodule // dsp_core_rx diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index f5271a207..3b05a4a08 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -15,7 +15,7 @@ module rx_frontend reg [15:0] adc_i, adc_q; wire [17:0] adc_i_ofs, adc_q_ofs; wire [35:0] corr_i, corr_q; - wire [17:0] scale_i, scale_q; + wire [17:0] mag_corr,phase_corr; wire [7:0] muxctrl; wire [23:0] i_final, q_final; @@ -41,11 +41,11 @@ module rx_frontend setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(scale_i),.changed()); + .in(set_data),.out(mag_corr),.changed()); setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(scale_q),.changed()); + .in(set_data),.out(phase_corr),.changed()); rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -55,12 +55,12 @@ module rx_frontend (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .in({adc_q,2'b00}),.out(adc_q_ofs)); - MULT18X18S mult_i - (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) ); - - MULT18X18S mult_q - (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); + MULT18X18S mult_mag_corr + (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); + MULT18X18S mult_phase_corr + (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); + add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final)); diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 691b60c1c..151ac27ae 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -604,7 +604,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -632,7 +632,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); 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