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-rw-r--r--usrp2/control_lib/Makefile.srcs5
-rw-r--r--usrp2/control_lib/newfifo/packet_generator.v59
-rw-r--r--usrp2/fifo/Makefile.srcs5
-rw-r--r--usrp2/fifo/fifo36_mux.v37
-rw-r--r--usrp2/fifo/fifo_pacer.v (renamed from usrp2/control_lib/newfifo/fifo_pacer.v)0
-rw-r--r--usrp2/fifo/packet32_tb.v (renamed from usrp2/control_lib/newfifo/packet32_tb.v)0
-rw-r--r--usrp2/fifo/packet_generator.v83
-rw-r--r--usrp2/fifo/packet_generator32.v (renamed from usrp2/control_lib/newfifo/packet_generator32.v)2
-rw-r--r--usrp2/fifo/packet_tb.v (renamed from usrp2/control_lib/newfifo/packet_tb.v)0
-rw-r--r--usrp2/fifo/packet_verifier.v (renamed from usrp2/control_lib/newfifo/packet_verifier.v)2
-rw-r--r--usrp2/fifo/packet_verifier32.v (renamed from usrp2/control_lib/newfifo/packet_verifier32.v)0
-rw-r--r--usrp2/gpmc/fifo_to_gpmc_async.v5
-rw-r--r--usrp2/gpmc/gpmc_async.v120
-rw-r--r--usrp2/top/u1e/u1e_core.v99
14 files changed, 243 insertions, 174 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index 5ae185ee8..751b40828 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -50,9 +50,4 @@ bootram.v \
nsgpio16LE.v \
settings_bus_16LE.v \
atr_controller16.v \
-newfifo/fifo_pacer.v \
-newfifo/packet_generator32.v \
-newfifo/packet_generator.v \
-newfifo/packet_verifier32.v \
-newfifo/packet_verifier.v \
))
diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
deleted file mode 100644
index 6e8b45ccd..000000000
--- a/usrp2/control_lib/newfifo/packet_generator.v
+++ /dev/null
@@ -1,59 +0,0 @@
-
-
-module packet_generator
- (input clk, input reset, input clear,
- output reg [7:0] data_o, output sof_o, output eof_o,
- output src_rdy_o, input dst_rdy_i);
-
- localparam len = 32'd2000;
-
- reg [31:0] state;
- reg [31:0] seq;
- wire [31:0] crc_out;
- wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
-
-
- always @(posedge clk)
- if(reset | clear)
- seq <= 0;
- else
- if(eof_o & src_rdy_o & dst_rdy_i)
- seq <= seq + 1;
-
- always @(posedge clk)
- if(reset | clear)
- state <= 0;
- else
- if(src_rdy_o & dst_rdy_i)
- if(state == (len - 1))
- state <= 32'hFFFF_FFFC;
- else
- state <= state + 1;
-
- always @*
- case(state)
- 0 : data_o <= len[7:0];
- 1 : data_o <= len[15:8];
- 2 : data_o <= len[23:16];
- 3 : data_o <= len[31:24];
- 4 : data_o <= seq[7:0];
- 5 : data_o <= seq[15:8];
- 6 : data_o <= seq[23:16];
- 7 : data_o <= seq[31:24];
- 32'hFFFF_FFFC : data_o <= crc_out[31:24];
- 32'hFFFF_FFFD : data_o <= crc_out[23:16];
- 32'hFFFF_FFFE : data_o <= crc_out[15:8];
- 32'hFFFF_FFFF : data_o <= crc_out[7:0];
- default : data_o <= state[7:0];
- endcase // case (state)
-
- assign src_rdy_o = 1;
- assign sof_o = (state == 0);
- assign eof_o = (state == 32'hFFFF_FFFF);
-
- wire clear_crc = eof_o & src_rdy_o & dst_rdy_i;
-
- crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o),
- .calc(calc_crc), .crc_out(crc_out), .match());
-
-endmodule // packet_generator
diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index f0b5b7bae..c1287cd5c 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -28,4 +28,9 @@ fifo36_demux.v \
packet_router.v \
splitter36.v \
valve36.v \
+fifo_pacer.v \
+packet_generator32.v \
+packet_generator.v \
+packet_verifier32.v \
+packet_verifier.v \
))
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
index c6fd40f27..7f0f803ff 100644
--- a/usrp2/fifo/fifo36_mux.v
+++ b/usrp2/fifo/fifo36_mux.v
@@ -10,6 +10,19 @@ module fifo36_mux
input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+ wire [35:0] data0_int, data1_int;
+ wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int;
+
+ fifo_short #(.WIDTH(36)) mux_fifo_in0
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o),
+ .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int));
+
+ fifo_short #(.WIDTH(36)) mux_fifo_in1
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o),
+ .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int));
+
localparam MUX_IDLE0 = 0;
localparam MUX_DATA0 = 1;
localparam MUX_IDLE1 = 2;
@@ -17,8 +30,8 @@ module fifo36_mux
reg [1:0] state;
- wire eof0 = data0_i[33];
- wire eof1 = data1_i[33];
+ wire eof0 = data0_int[33];
+ wire eof1 = data1_int[33];
wire [35:0] data_int;
wire src_rdy_int, dst_rdy_int;
@@ -29,33 +42,33 @@ module fifo36_mux
else
case(state)
MUX_IDLE0 :
- if(src0_rdy_i)
+ if(src0_rdy_int)
state <= MUX_DATA0;
- else if(src1_rdy_i)
+ else if(src1_rdy_int)
state <= MUX_DATA1;
MUX_DATA0 :
- if(src0_rdy_i & dst_rdy_int & eof0)
+ if(src0_rdy_int & dst_rdy_int & eof0)
state <= prio ? MUX_IDLE0 : MUX_IDLE1;
MUX_IDLE1 :
- if(src1_rdy_i)
+ if(src1_rdy_int)
state <= MUX_DATA1;
- else if(src0_rdy_i)
+ else if(src0_rdy_int)
state <= MUX_DATA0;
MUX_DATA1 :
- if(src1_rdy_i & dst_rdy_int & eof1)
+ if(src1_rdy_int & dst_rdy_int & eof1)
state <= MUX_IDLE0;
default :
state <= MUX_IDLE0;
endcase // case (state)
- assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0;
- assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0;
- assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
- assign data_int = (state==MUX_DATA0) ? data0_i : data1_i;
+ assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
+ assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0;
+ assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
+ assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
fifo_short #(.WIDTH(36)) mux_fifo
(.clk(clk), .reset(reset), .clear(clear),
diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/fifo/fifo_pacer.v
index 1bf03ab6e..1bf03ab6e 100644
--- a/usrp2/control_lib/newfifo/fifo_pacer.v
+++ b/usrp2/fifo/fifo_pacer.v
diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/fifo/packet32_tb.v
index 82bb09c29..82bb09c29 100644
--- a/usrp2/control_lib/newfifo/packet32_tb.v
+++ b/usrp2/fifo/packet32_tb.v
diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v
new file mode 100644
index 000000000..2ae911e24
--- /dev/null
+++ b/usrp2/fifo/packet_generator.v
@@ -0,0 +1,83 @@
+
+
+module packet_generator
+ (input clk, input reset, input clear,
+ output reg [7:0] data_o, output sof_o, output eof_o,
+ input [127:0] header,
+ output src_rdy_o, input dst_rdy_i);
+
+ localparam len = 32'd2000;
+
+ reg [31:0] state;
+ reg [31:0] seq;
+ reg [31:0] crc_out;
+ wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+
+
+ always @(posedge clk)
+ if(reset | clear)
+ seq <= 0;
+ else
+ if(eof_o & src_rdy_o & dst_rdy_i)
+ seq <= seq + 1;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= 0;
+ else
+ if(src_rdy_o & dst_rdy_i)
+ if(state == (len - 1))
+ state <= 32'hFFFF_FFFC;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : data_o <= len[31:24];
+ 1 : data_o <= len[23:16];
+ 2 : data_o <= len[15:8];
+ 3 : data_o <= len[7:0];
+ 4 : data_o <= seq[31:24];
+ 5 : data_o <= seq[23:16];
+ 6 : data_o <= seq[15:8];
+ 7 : data_o <= seq[7:0];
+ 8 : data_o <= header[7:0];
+ 9 : data_o <= header[15:8];
+ 10 : data_o <= header[23:16];
+ 11 : data_o <= header[31:24];
+ 12 : data_o <= header[39:32];
+ 13 : data_o <= header[47:40];
+ 14 : data_o <= header[55:48];
+ 15 : data_o <= header[63:56];
+ 16 : data_o <= header[71:64];
+ 17 : data_o <= header[79:72];
+ 18 : data_o <= header[87:80];
+ 19 : data_o <= header[95:88];
+ 20 : data_o <= header[103:96];
+ 21 : data_o <= header[111:104];
+ 22 : data_o <= header[119:112];
+ 23 : data_o <= header[127:120];
+
+ 32'hFFFF_FFFC : data_o <= crc_out[31:24];
+ 32'hFFFF_FFFD : data_o <= crc_out[23:16];
+ 32'hFFFF_FFFE : data_o <= crc_out[15:8];
+ 32'hFFFF_FFFF : data_o <= crc_out[7:0];
+ default : data_o <= state[7:0];
+ endcase // case (state)
+
+ assign src_rdy_o = 1;
+ assign sof_o = (state == 0);
+ assign eof_o = (state == 32'hFFFF_FFFF);
+
+ wire clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+
+// crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o),
+// .calc(calc_crc), .crc_out(crc_out), .match());
+ always @(posedge clk)
+ if(reset | clear | clear_crc)
+ crc_out <= 0;
+ else
+ if(calc_crc)
+ crc_out <= crc_out + data_o;
+
+endmodule // packet_generator
diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/fifo/packet_generator32.v
index 6f8004964..1dc57191d 100644
--- a/usrp2/control_lib/newfifo/packet_generator32.v
+++ b/usrp2/fifo/packet_generator32.v
@@ -2,6 +2,7 @@
module packet_generator32
(input clk, input reset, input clear,
+ input [127:0] header,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
wire [7:0] ll_data;
@@ -10,6 +11,7 @@ module packet_generator32
packet_generator pkt_gen
(.clk(clk), .reset(reset), .clear(clear),
.data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+ .header(header),
.src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
ll8_to_fifo36 ll8_to_f36
diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/fifo/packet_tb.v
index 3c423d2ba..3c423d2ba 100644
--- a/usrp2/control_lib/newfifo/packet_tb.v
+++ b/usrp2/fifo/packet_tb.v
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/fifo/packet_verifier.v
index b49ad1bbb..21a4c136e 100644
--- a/usrp2/control_lib/newfifo/packet_verifier.v
+++ b/usrp2/fifo/packet_verifier.v
@@ -18,7 +18,7 @@ module packet_verifier
reg [31:0] length;
wire first_byte, last_byte;
reg second_byte, last_byte_d1;
-
+ wire match_crc;
wire calc_crc = src_rdy_i & dst_rdy_o;
crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i),
diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/fifo/packet_verifier32.v
index 06a13d242..06a13d242 100644
--- a/usrp2/control_lib/newfifo/packet_verifier32.v
+++ b/usrp2/fifo/packet_verifier32.v
diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
index cf8b6e861..9a8e37ce9 100644
--- a/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -1,9 +1,4 @@
-// Assumes an asynchronous GPMC cycle
-// If a packet bigger or smaller than we are told is sent, behavior is undefined.
-// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
-// If there is a bus error, we should be reset
-
module fifo_to_gpmc_async
(input clk, input reset, input clear,
input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index 23bad56ae..02bf45b8a 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -1,7 +1,9 @@
//////////////////////////////////////////////////////////////////////////////////
module gpmc_async
- #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+ #(parameter TXFIFOSIZE = 11,
+ parameter RXFIFOSIZE = 11,
+ parameter BUSDEBUG = 1)
(// GPMC signals
input arst,
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -21,7 +23,9 @@ module gpmc_async
input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
input [15:0] tx_frame_len, output [15:0] rx_frame_len,
-
+
+ output tx_underrun, output rx_overrun,
+ input [7:0] test_rate, input [3:0] test_ctrl,
output [31:0] debug
);
@@ -49,8 +53,8 @@ module gpmc_async
wire [17:0] tx18_data, tx18b_data;
wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
wire [15:0] tx_fifo_space;
- wire [35:0] tx36_data;
- wire tx36_src_rdy, tx36_dst_rdy;
+ wire [35:0] tx36_data, tx_data;
+ wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy;
gpmc_to_fifo_async gpmc_to_fifo_async
(.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
@@ -70,9 +74,9 @@ module gpmc_async
.f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
.datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
- .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+ .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy));
// ////////////////////////////////////////////
// RX Data Path
@@ -80,13 +84,13 @@ module gpmc_async
wire [17:0] rx18_data, rx18b_data;
wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
wire [15:0] rx_fifo_space;
- wire [35:0] rx36_data;
- wire rx36_src_rdy, rx36_dst_rdy;
+ wire [35:0] rx36_data, rx_data;
+ wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy;
wire dummy;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
.dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE
@@ -125,6 +129,100 @@ module gpmc_async
.wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
.wb_ack_i(wb_ack_i) );
- assign debug = pkt_count;
+// assign debug = pkt_count;
+
+ // ////////////////////////////////////////////
+ // Test support, traffic generator, loopback, etc.
+
+ // RX side muxes test data into the same stream
+ wire [35:0] timedrx_data, loopbackrx_data, testrx_data;
+ wire [35:0] timedtx_data, loopbacktx_data, testtx_data;
+ wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy,
+ testrx_src_rdy, testrx_dst_rdy;
+ wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy,
+ testtx_src_rdy, testtx_dst_rdy;
+ wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int;
+
+ wire [31:0] total, crc_err, seq_err, len_err;
+ wire sel_testtx = test_ctrl[0];
+ wire sel_loopbacktx = test_ctrl[1];
+ wire pkt_src_enable = test_ctrl[2];
+ wire pkt_sink_enable = test_ctrl[3];
+
+ fifo36_mux rx_test_mux_lvl_1
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy),
+ .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy),
+ .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy));
+
+ fifo36_mux rx_test_mux_lvl_2
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy),
+ .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
+ .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+ fifo_short #(.WIDTH(36)) loopback_fifo
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
+ .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
+ .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
+ // Crossbar used as a demux for switching TX stream to main DSP or to test logic
+ crossbar36 tx_crossbar_lvl_1
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .cross(sel_testtx),
+ .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
+ .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input
+ .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
+ .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) );
+
+ crossbar36 tx_crossbar_lvl_2
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .cross(sel_loopbacktx),
+ .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy),
+ .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input
+ .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy),
+ .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
+
+ // Fixed rate TX traffic consumer
+ fifo_pacer tx_pacer
+ (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable),
+ .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
+ .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
+ .underrun(tx_underrun), .overrun());
+
+ packet_verifier32 pktver32
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int),
+ .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+ // Fixed rate RX traffic generator
+ packet_generator32 pktgen32
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .header({len_err,seq_err,crc_err,total}),
+ .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int));
+
+ fifo_pacer rx_pacer
+ (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable),
+ .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
+ .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
+ .underrun(), .overrun(rx_overrun));
+
+ // FIXME -- hook up crossbar controls
+ // // FIXME -- collect error stats
+ // FIXME -- set rates and enables on pacers
+ // FIXME -- make sure packet completes before we shutoff
+ // FIXME -- handle overrun and underrun
+
+wire [0:17] dummy18;
+
+assign debug = {8'd0,
+ test_rate,
+ pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
+ timedrx_src_rdy, timedrx_dst_rdy,
+ testrx_src_rdy, testrx_dst_rdy,
+ rx_src_rdy, rx_dst_rdy,
+ rx36_src_rdy, rx36_dst_rdy,
+ rx18_src_rdy, rx18_dst_rdy,
+ rx18b_src_rdy, rx18b_dst_rdy};
+
endmodule // gpmc_async
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 7d5924bea..a5a477202 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,9 +1,5 @@
-//`define LOOPBACK 1
-//`define TIMED 1
-`define DSP 1
-
module u1e_core
(input clk_fpga, input rst_fpga,
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -48,13 +44,18 @@ module u1e_core
wire pps_int;
wire [63:0] vita_time, vita_time_pps;
reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+ wire [7:0] test_rate;
+ wire [3:0] test_ctrl;
wire [7:0] set_addr;
wire [31:0] set_data;
wire set_stb;
wire [31:0] debug_vt;
-
+ wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
+ assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
+ assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+
setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(global_reset));
@@ -79,7 +80,6 @@ module u1e_core
tx_err_src_rdy, tx_err_dst_rdy;
reg [15:0] tx_frame_len;
wire [15:0] rx_frame_len;
- wire [7:0] rate;
wire bus_error;
wire clear_tx, clear_rx;
@@ -111,62 +111,15 @@ module u1e_core
.rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
.tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+ .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
+
+ .test_rate(test_rate), .test_ctrl(test_ctrl),
.debug(debug_gpmc));
wire rx_sof = rx_data[32];
wire rx_eof = rx_data[33];
wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
-`ifdef LOOPBACK
- wire [7:0] WHOAMI = 1;
-
- fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
- .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
- assign tx_underrun = 0;
- assign rx_overrun = 0;
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // LOOPBACK
-
-`ifdef TIMED
- wire [7:0] WHOAMI = 2;
-
- // TX side
- wire tx_enable;
-
- fifo_pacer tx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
- .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
- .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
- .underrun(tx_underrun), .overrun());
-
- packet_verifier32 pktver32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
- .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
- // RX side
- wire rx_enable;
-
- packet_generator32 pktgen32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
-
- fifo_pacer rx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
- .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
- .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
- .underrun(), .overrun(rx_overrun));
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // `ifdef TIMED
-
-`ifdef DSP
- wire [7:0] WHOAMI = 0;
-
wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug;
// /////////////////////////////////////////////////////////////////////////
@@ -189,7 +142,7 @@ module u1e_core
vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .vita_time(vita_time), .overrun(rx_overrun),
+ .vita_time(vita_time), .overrun(rx_overrun_dsp),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
.debug_rx(vrc_debug));
@@ -225,29 +178,12 @@ module u1e_core
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(tx_i_int),.dac_b(tx_q_int),
- .underrun(underrun), .run(run_tx),
+ .underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
assign tx_i = tx_i_int[15:2];
assign tx_q = tx_q_int[15:2];
-`else // !`ifdef DSP
- // Dummy DSP signal generator for test purposes
- wire [23:0] tx_i_int, tx_q_int;
- wire [23:0] freq = {reg_test,8'd0};
- reg [23:0] phase;
-
- always @(posedge wb_clk)
- phase <= phase + freq;
-
- cordic_z24 #(.bitwidth(24)) tx_cordic
- (.clock(wb_clk), .reset(wb_rst), .enable(1),
- .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
-
- assign tx_i = tx_i_int[23:10];
- assign tx_q = tx_q_int[23:10];
-`endif // !`ifdef DSP
-
// /////////////////////////////////////////////////////////////////////////////////////
// Wishbone Intercon, single master
wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
@@ -320,7 +256,6 @@ module u1e_core
// Slave 0, Misc LEDs, Switches, controls
localparam REG_LEDS = 7'd0; // out
- localparam REG_SWITCHES = 7'd2; // in
localparam REG_CGEN_CTRL = 7'd4; // out
localparam REG_CGEN_ST = 7'd6; // in
localparam REG_TEST = 7'd8; // out
@@ -353,20 +288,18 @@ module u1e_core
xfer_rate <= s0_dat_mosi;
endcase // case (s0_adr[6:0])
- assign tx_enable = xfer_rate[15];
- assign rx_enable = xfer_rate[14];
- assign rate = xfer_rate[7:0];
+ assign test_ctrl = xfer_rate[11:8];
+ assign test_rate = xfer_rate[7:0];
assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds :
- (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
(s0_adr[6:0] == REG_TEST) ? reg_test :
(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
- (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+ (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } :
16'hBEEF;
assign s0_ack = s0_stb & s0_cyc;
@@ -475,10 +408,14 @@ module u1e_core
assign debug_clk = { EM_CLK, clk_fpga };
+/*
assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
{ tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
{ EM_D } };
+*/
+ assign debug = debug_gpmc;
+
assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]},
{2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 10:40:52 +0000