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-rw-r--r--usrp2/gpmc/gpmc.v61
-rw-r--r--usrp2/gpmc/gpmc_to_fifo_async.v2
-rw-r--r--usrp2/gpmc/gpmc_to_fifo_sync.v57
-rw-r--r--usrp2/top/u1e/Makefile1
4 files changed, 95 insertions, 26 deletions
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 2715414b3..d6a685bba 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -4,7 +4,8 @@ module gpmc
(// GPMC signals
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
-
+ output bus_error,
+
// GPIOs for FIFO signalling
output rx_have_data, output tx_have_space,
@@ -17,15 +18,15 @@ module gpmc
input fifo_clk, input fifo_rst,
output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-
+
output [31:0] debug
);
wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
- wire [15:0] EM_D_ram;
+ wire [15:0] EM_D_fifo;
wire [15:0] EM_D_wb;
- assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb;
+ assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
// CS4 is RAM_2PORT for DATA PATH (high-speed data)
// Writes go into one RAM, reads come from the other
@@ -37,19 +38,22 @@ module gpmc
wire [17:0] tx18_data, tx18b_data;
wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
wire [15:0] tx_fifo_space, tx_frame_len;
-
+
assign tx_frame_len = 10;
+ wire arst;
- gpmc_to_fifo gpmc_to_fifo
- (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
- .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+ gpmc_to_fifo_sync gpmc_to_fifo_sync
+ (.arst(arst),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
.data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
- .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space));
+ .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+ .bus_error(bus_error) );
- fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
- (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
- .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy));
+ fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+ (.wclk(EM_CLK), .datain(tx18_data),
+ .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+ .rclk(fifo_clk), .dataout(tx18b_data),
+ .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst));
fifo19_to_fifo36 f19_to_f36
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
@@ -59,21 +63,28 @@ module gpmc
// ////////////////////////////////////////////
// RX Data Path
- wire read_sel_rx, write_sel_rx, clear_rx;
- wire read_done_rx;
-
- edge_sync #(.POSEDGE(0))
- edge_sync_rx(.clk(wb_clk), .rst(wb_rst),
- .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_rx));
+
+ wire [17:0] rx18_data, rx18b_data;
+ wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+ wire [15:0] rx_fifo_space, rx_frame_len;
- ram_2port_mixed_width buffer_rx
- (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_rx,EM_A}), .di16(0), .do16(EM_D_ram),
- .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_rx,write_addr}), .di32(write_data), .do32());
+ fifo36_to_fifo18 f18_to_f36
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+ .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+ .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
- dbsm dbsm_rx(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .read_sel(read_sel_rx), .read_ready(rx_have_data), .read_done(read_done_rx),
- .write_sel(write_sel_rx), .write_ready(write_ready), .write_done(write_done));
+ fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo
+ (.wclk(fifo_clk), .datain(rx18_data),
+ .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+ .rclk(EM_CLK), .dataout(rx18b_data),
+ .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst));
+ fifo_to_gpmc_sync fifo_to_gpmc_sync
+ (.arst(arst),
+ .data_i(tx18b_data), .src_rdy_i(tx18b_src_rdy), .dst_rdy_o(tx18b_dst_rdy),
+ .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+ .fifo_ready(rx_have_data) );
+
// ////////////////////////////////////////////
// Control path on CS6
diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v
index c47d69d7d..a8068022f 100644
--- a/usrp2/gpmc/gpmc_to_fifo_async.v
+++ b/usrp2/gpmc/gpmc_to_fifo_async.v
@@ -1,6 +1,6 @@
module gpmc_to_fifo_async
- (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE,
+ (input [15:0] EM_D, input [1:0] EM_NBE,
input EM_NCS, input EM_NWE,
input fifo_clk, input fifo_rst,
diff --git a/usrp2/gpmc/gpmc_to_fifo_sync.v b/usrp2/gpmc/gpmc_to_fifo_sync.v
new file mode 100644
index 000000000..688de0e17
--- /dev/null
+++ b/usrp2/gpmc/gpmc_to_fifo_sync.v
@@ -0,0 +1,57 @@
+
+// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams
+// If a packet bigger or smaller than we are told is sent, behavior is undefined.
+// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+// If there is a bus error, we should be reset
+
+module gpmc_to_fifo_sync
+ (input arst,
+ input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE,
+ input EM_NCS, input EM_NWE,
+ output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
+ input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready,
+ output reg bus_error);
+
+ reg [10:0] counter;
+ wire first_write = (counter == 0);
+ wire last_write = ((counter+1) == frame_len);
+ wire do_write = ~EM_NCS & ~EM_NWE;
+
+ always @(posedge EM_CLK or posedge arst)
+ if(arst)
+ data_o <= 0;
+ else if(do_write)
+ begin
+ data_o[15:0] <= EM_D;
+ data_o[16] <= first_write;
+ data_o[17] <= last_write;
+ // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME
+ end
+
+ always @(posedge EM_CLK or posedge arst)
+ if(arst)
+ src_rdy_o <= 0;
+ else if(do_write & ~bus_error) // Don't put junk in if there is a bus error
+ src_rdy_o <= 1;
+ else
+ src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i
+
+ always @(posedge EM_CLK or posedge arst)
+ if(arst)
+ counter <= 0;
+ else if(do_write)
+ if(last_write)
+ counter <= 0;
+ else
+ counter <= counter + 1;
+
+ assign fifo_ready = first_write & (fifo_space > frame_len);
+
+ always @(posedge EM_CLK or posedge arst)
+ if(arst)
+ bus_error <= 0;
+ else if(src_rdy_o & ~dst_rdy_i)
+ bus_error <= 1;
+ // must be reset to make the error go away
+
+endmodule // gpmc_to_fifo_sync
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index ca4d9ce89..057de64cf 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -179,6 +179,7 @@ gpmc/gpmc.v \
gpmc/edge_sync.v \
gpmc/dbsm.v \
gpmc/gpmc_to_fifo_async.v \
+gpmc/gpmc_to_fifo_sync.v \
gpmc/gpmc_wb.v \
top/u1e/u1e_core.v \
top/u1e/u1e.ucf \
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 15:55:17 +0000