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-rw-r--r--usrp2/fifo/Makefile.srcs2
-rw-r--r--usrp2/fifo/fifo36_demux.v50
-rw-r--r--usrp2/fifo/fifo36_mux.v57
-rw-r--r--usrp2/sdr_lib/dsp_core_tx.v4
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v17
-rwxr-xr-xusrp2/vrt/vita_rx.build2
-rw-r--r--usrp2/vrt/vita_rx_control.v21
-rw-r--r--usrp2/vrt/vita_rx_framer.v47
-rw-r--r--usrp2/vrt/vita_rx_tb.v11
-rw-r--r--usrp2/vrt/vita_tx_deframer.v2
10 files changed, 180 insertions, 33 deletions
diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index 22867da7e..c66979132 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -20,4 +20,6 @@ fifo19_to_ll8.v \
ll8_to_fifo19.v \
fifo36_to_fifo19.v \
fifo19_to_fifo36.v \
+fifo36_mux.v \
+fifo36_demux.v \
))
diff --git a/usrp2/fifo/fifo36_demux.v b/usrp2/fifo/fifo36_demux.v
new file mode 100644
index 000000000..a54759d4d
--- /dev/null
+++ b/usrp2/fifo/fifo36_demux.v
@@ -0,0 +1,50 @@
+
+// Demux packets from a fifo based on the contents of the first line
+// If first line matches the parameter and mask, send to data1, otherwise send to data0
+
+module fifo36_demux
+ #(parameter match_data = 0,
+ parameter match_mask = 0)
+ (input clk, input reset, input clear,
+ input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+ output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
+ output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
+
+ localparam DMX_IDLE = 0;
+ localparam DMX_DATA0 = 1;
+ localparam DMX_DATA1 = 2;
+
+ reg [1:0] state;
+
+ wire match = |( (data_i ^ match_data) & match_mask );
+ wire eof = data_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= DMX_IDLE;
+ else
+ case(state)
+ DMX_IDLE :
+ if(src_rdy_i)
+ if(match)
+ state <= DMX_DATA1;
+ else
+ state <= DMX_DATA0;
+ DMX_DATA0 :
+ if(src_rdy_i & dst0_rdy_i & eof)
+ state <= DMX_IDLE;
+ DMX_DATA1 :
+ if(src_rdy_i & dst1_rdy_i & eof)
+ state <= DMX_IDLE;
+ default :
+ state <= DMX_IDLE;
+ endcase // case (state)
+
+ assign dst_rdy_o = (state==DMX_IDLE) ? 0 : (state==DMX_DATA0) ? dst0_rdy_i : dst1_rdy_i;
+ assign src0_rdy_o = (state==DMX_DATA0) ? src_rdy_i : 0;
+ assign src1_rdy_o = (state==DMX_DATA1) ? src_rdy_i : 0;
+
+ assign data0_o = data_i;
+ assign data1_o = data_i;
+
+endmodule // fifo36_demux
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
new file mode 100644
index 000000000..04ec5abe8
--- /dev/null
+++ b/usrp2/fifo/fifo36_mux.v
@@ -0,0 +1,57 @@
+
+// Mux packets from multiple FIFO interfaces onto a single one.
+// Can alternate or give priority to one port (port 0)
+// In prio mode, port 1 will never get access if port 0 is always busy
+
+module fifo36_mux
+ #(parameter prio = 0)
+ (input clk, input reset, input clear,
+ input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+ input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ localparam MUX_IDLE0 = 0;
+ localparam MUX_DATA0 = 1;
+ localparam MUX_IDLE1 = 2;
+ localparam MUX_DATA1 = 3;
+
+ reg [1:0] state;
+
+ wire eof0 = data0_i[33];
+ wire eof1 = data1_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= MUX_IDLE0;
+ else
+ case(state)
+ MUX_IDLE0 :
+ if(src0_rdy_i)
+ state <= MUX_DATA0;
+ else if(src1_rdy_i)
+ state <= MUX_DATA1;
+
+ MUX_DATA0 :
+ if(src0_rdy_i & dst_rdy_i & eof0)
+ state <= prio ? MUX_IDLE0 : MUX_IDLE1;
+
+ MUX_IDLE1 :
+ if(src1_rdy_i)
+ state <= MUX_DATA1;
+ else if(src0_rdy_i)
+ state <= MUX_DATA0;
+
+ MUX_DATA1 :
+ if(src1_rdy_i & dst_rdy_i & eof1)
+ state <= MUX_IDLE0;
+
+ default :
+ state <= MUX_IDLE0;
+ endcase // case (state)
+
+ assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
+ assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
+ assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
+ assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i;
+
+endmodule // fifo36_demux
diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v
index 22d3d44a3..79d92c9b3 100644
--- a/usrp2/sdr_lib/dsp_core_tx.v
+++ b/usrp2/sdr_lib/dsp_core_tx.v
@@ -29,11 +29,11 @@ module dsp_core_tx
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({scale_i,scale_q}),.changed());
- setting_reg #(.my_addr(BASE+2)) sr_2
+ setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
- setting_reg #(.my_addr(BASE+4)) sr_4
+ setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({dacmux_b,dacmux_a}),.changed());
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index 33e9dbcd9..e3f1558a1 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -182,6 +182,11 @@ module u2_core
wire [31:0] irq;
wire [63:0] vita_time;
+ wire run_rx, run_tx;
+ reg run_rx_d1;
+ always @(posedge dsp_clk)
+ run_rx_d1 <= run_rx;
+
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
localparam dw = 32; // Data bus width
@@ -511,12 +516,13 @@ module u2_core
// In Rev3 there are only 6 leds, and the highest one is on the ETH connector
wire [7:0] led_src, led_sw;
- wire [7:0] led_hw = {clk_status,serdes_link_up};
+ wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0};
setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(led_sw),.changed());
- setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(led_src),.changed());
+
+ setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110))
+ sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
assign leds = (led_src & led_hw) | (~led_src & led_sw);
@@ -567,11 +573,6 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// ATR Controller, Slave #11
- wire run_rx, run_tx;
- reg run_rx_d1;
- always @(posedge dsp_clk)
- run_rx_d1 <= run_rx;
-
atr_controller atr_controller
(.clk_i(wb_clk),.rst_i(wb_rst),
.adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build
index f6d2d75a3..010d1be6e 100755
--- a/usrp2/vrt/vita_rx.build
+++ b/usrp2/vrt/vita_rx.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index 669b8299d..93673d292 100644
--- a/usrp2/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
@@ -31,13 +31,13 @@ module vita_rx_control
wire [63:0] rcvtime_pre;
reg [63:0] rcvtime;
- wire [29:0] numlines_pre;
- wire send_imm_pre, chain_pre;
- reg send_imm, chain;
+ wire [28:0] numlines_pre;
+ wire send_imm_pre, chain_pre, reload_pre;
+ reg send_imm, chain, reload;
wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
reg sc_pre2;
wire [33:0] fifo_line;
- reg [29:0] lines_left;
+ reg [28:0] lines_left, lines_total;
reg [2:0] ibs_state;
wire now, early, late;
wire sample_fifo_in_rdy;
@@ -67,7 +67,7 @@ module vita_rx_control
shortfifo #(.WIDTH(96)) commandfifo
(.clk(clk),.rst(reset),.clear(clear_int),
.datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
- .dataout({send_imm_pre,chain_pre,numlines_pre,rcvtime_pre}),
+ .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
.read(read_ctrl), .empty(empty_ctrl),
.occupied(command_queue_len), .space() );
@@ -111,9 +111,11 @@ module vita_rx_control
begin
ibs_state <= IBS_IDLE;
lines_left <= 0;
+ lines_total <= 0;
rcvtime <= 0;
send_imm <= 0;
chain <= 0;
+ reload <= 0;
end
else
case(ibs_state)
@@ -121,10 +123,12 @@ module vita_rx_control
if(~empty_ctrl)
begin
lines_left <= numlines_pre;
+ lines_total <= numlines_pre;
rcvtime <= rcvtime_pre;
ibs_state <= IBS_WAITING;
send_imm <= send_imm_pre;
chain <= chain_pre;
+ reload <= reload_pre;
end
IBS_WAITING :
if(go_now)
@@ -141,14 +145,21 @@ module vita_rx_control
if(lines_left == 1)
if(~chain)
ibs_state <= IBS_IDLE;
+ else if(empty_ctrl & reload)
+ begin
+ ibs_state <= IBS_RUNNING;
+ lines_left <= lines_total;
+ end
else if(empty_ctrl)
ibs_state <= IBS_BROKENCHAIN;
else
begin
lines_left <= numlines_pre;
+ lines_total <= numlines_pre;
rcvtime <= rcvtime_pre;
send_imm <= send_imm_pre;
chain <= chain_pre;
+ reload <= reload_pre;
if(numlines_pre == 0) // If we are told to stop here
ibs_state <= IBS_IDLE;
else
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index f3a81664a..fd82263d0 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -99,7 +99,7 @@ module vita_rx_framer
localparam VITA_ERR_TICS = 12;
localparam VITA_ERR_TICS2 = 13;
localparam VITA_ERR_PAYLOAD = 14;
- localparam VITA_ERR_TRAILER = 15;
+ localparam VITA_ERR_TRAILER = 15; // Extension context packets have no trailer
always @(posedge clk)
if(reset | clear_pkt_count)
@@ -107,17 +107,30 @@ module vita_rx_framer
else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
pkt_count <= pkt_count + 1;
+ wire has_streamid = vita_header[28];
+ wire has_trailer = vita_header[26];
+ reg trl_eob;
+
always @*
case(vita_state)
- VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,vita_header[31:20],pkt_count,vita_pkt_len};
- VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
- VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
- VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
- VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+ // Data packets are IF Data packets with or w/o streamid, no classid, with trailer
+ VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len};
+ VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+ VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+ VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
+ VITA_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
- VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o};
- VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer};
- VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+ VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer[31:21],1'b1,vita_trailer[19:9],trl_eob,8'd0};
+
+ // Error packets are Extension Context packets, which have no trailer
+ VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,4'b0101,4'b0000,vita_header[23:20],pkt_count,16'd6};
+ VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+ VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+ VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+ VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o};
+ //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+
default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
endcase // case (vita_state)
@@ -141,6 +154,11 @@ module vita_rx_framer
end
else if(pkt_fifo_rdy)
case(vita_state)
+ VITA_HEADER :
+ if(has_streamid)
+ vita_state <= VITA_STREAMID;
+ else
+ vita_state <= VITA_SECS;
VITA_PAYLOAD :
if(sample_fifo_src_rdy_i)
begin
@@ -148,6 +166,7 @@ module vita_rx_framer
begin
sample_phase <= 0;
sample_ctr <= sample_ctr + 1;
+ trl_eob <= flags_fifo_o[0];
if(sample_ctr == samples_per_packet)
vita_state <= VITA_TRAILER;
if(|flags_fifo_o) // end early if any flag is set
@@ -155,8 +174,10 @@ module vita_rx_framer
end
else
sample_phase <= sample_phase + 1;
- end
- VITA_TRAILER, VITA_ERR_TRAILER :
+ end // if (sample_fifo_src_rdy_i)
+ VITA_ERR_PAYLOAD :
+ vita_state <= VITA_IDLE;
+ VITA_TRAILER :
vita_state <= VITA_IDLE;
default :
vita_state <= vita_state + 1;
@@ -172,7 +193,7 @@ module vita_rx_framer
VITA_PAYLOAD :
// Write if sample ready and no error flags
req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
- VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
+ VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
req_write_pkt_fifo <= 1;
default :
req_write_pkt_fifo <= 0;
@@ -192,7 +213,7 @@ module vita_rx_framer
( ((vita_state==VITA_PAYLOAD) &
(sample_phase == (numchan-4'd1)) &
~|flags_fifo_o[3:1]) |
- (vita_state==VITA_ERR_TRAILER));
+ (vita_state==VITA_ERR_PAYLOAD));
assign debug_rx = vita_state;
diff --git a/usrp2/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v
index b4fda9622..3e01e2ee2 100644
--- a/usrp2/vrt/vita_rx_tb.v
+++ b/usrp2/vrt/vita_rx_tb.v
@@ -3,8 +3,8 @@
module vita_rx_tb;
localparam DECIM = 8'd4;
- localparam MAXCHAN=4;
- localparam NUMCHAN=4;
+ localparam MAXCHAN=1;
+ localparam NUMCHAN=1;
reg clk = 0;
reg reset = 1;
@@ -94,7 +94,7 @@ module vita_rx_tb;
@(posedge clk);
write_setting(4,32'hDEADBEEF); // VITA header
write_setting(5,32'hF00D1234); // VITA streamid
- write_setting(6,32'h98765432); // VITA trailer
+ write_setting(6,32'hF0000000); // VITA trailer
write_setting(7,8); // Samples per VITA packet
write_setting(8,NUMCHAN); // Samples per VITA packet
queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
@@ -111,8 +111,13 @@ module vita_rx_tb;
queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time
queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late
+ #100000;
+ $display("\nChained, break chain\n");
queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain
#100000;
+ $display("\nSingle packet\n");
+ queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
+ #100000;
$display("\nEnd chain with zero samples, shouldn't error\n");
queue_rx_cmd(1,1,8,32'h0,32'h0); // chained
queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 220d3b061..3b95f5902 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -22,7 +22,7 @@ module vita_tx_deframer
);
wire [1:0] numchan;
- setting_reg #(.my_addr(BASE), .at_reset(0)) sr_numchan
+ setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 14:24:45 +0000