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-rw-r--r--usrp2/timing/time_64bit.v17
-rw-r--r--usrp2/top/u2_core/u2_core.v50
-rw-r--r--usrp2/top/u2_rev3/Makefile3
-rw-r--r--usrp2/vrt/vita_tx_control.v7
4 files changed, 43 insertions, 34 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 84f79645c..8ccde3f54 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -11,7 +11,8 @@ module time_64bit
localparam NEXT_SECS = 0;
localparam NEXT_TICKS = 1;
- localparam PPS_POL = 2;
+ localparam PPS_POLSRC = 2;
+ localparam PPS_IMM = 3;
localparam ROLLOVER = TICKS_PER_SEC - 1;
@@ -25,6 +26,8 @@ module time_64bit
wire set_on_pps_trig;
reg set_on_next_pps;
wire pps_polarity;
+ wire set_imm;
+ wire pps_source;
setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -34,9 +37,13 @@ module time_64bit
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
- setting_reg #(.my_addr(BASE+PPS_POL)) sr_pps_pol
+ setting_reg #(.my_addr(BASE+PPS_POLSRC)) sr_pps_polsrc
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(pps_polarity),.changed());
+ .in(set_data),.out({pps_source,pps_polarity}),.changed());
+
+ setting_reg #(.my_addr(BASE+PPS_IMM)) sr_pps_imm
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(set_imm),.changed());
reg [1:0] pps_del;
reg pps_reg_p, pps_reg_n, pps_reg;
@@ -59,7 +66,7 @@ module time_64bit
set_on_next_pps <= 0;
else if(set_on_pps_trig)
set_on_next_pps <= 1;
- else if(pps_edge)
+ else if(set_imm | pps_edge)
set_on_next_pps <= 0;
always @(posedge clk)
@@ -68,7 +75,7 @@ module time_64bit
seconds <= 32'd0;
ticks <= 32'd0;
end
- else if(pps_edge & set_on_next_pps)
+ else if((set_imm | pps_edge) & set_on_next_pps)
begin
seconds <= next_seconds_preset;
ticks <= next_ticks_preset;
diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v
index 78ddd515c..a9c97c869 100644
--- a/usrp2/top/u2_core/u2_core.v
+++ b/usrp2/top/u2_core/u2_core.v
@@ -141,10 +141,10 @@ module u2_core
localparam SR_RX_DSP = 160; // 16
localparam SR_RX_CTRL = 176; // 16
localparam SR_TIME64 = 192; // 3
+ localparam SR_SIMTIMER = 198; // 2
localparam SR_TX_DSP = 208; // 16
localparam SR_TX_CTRL = 224; // 16
-
wire [7:0] set_addr;
wire [31:0] set_data;
wire set_stb;
@@ -153,7 +153,8 @@ module u2_core
wire ram_loader_rst, wb_rst, dsp_rst;
wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
- wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+ wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+ wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
wire [31:0] debug_gpio_0, debug_gpio_1;
wire [31:0] atr_lines;
@@ -415,8 +416,8 @@ module u2_core
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
- .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
- .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
);
// /////////////////////////////////////////////////////////////////////////
@@ -496,8 +497,8 @@ module u2_core
assign irq= {{8'b0},
{8'b0},
- {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
- {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+ {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+ {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
@@ -506,13 +507,25 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// Master Timer, Slave #9
+ // No longer used, replaced with simple_timer below
+ /*
wire [31:0] master_time;
timer timer
(.wb_clk_i(wb_clk),.rst_i(wb_rst),
.cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
.we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
.sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
-
+ */
+ assign s9_ack = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Simple Timer interrupts
+
+ simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+ (.clk(wb_clk), .reset(wb_rst),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .onetime_int(onetime_int), .periodic_int(periodic_int));
+
// /////////////////////////////////////////////////////////////////////////
// UART, Slave #10
@@ -540,22 +553,9 @@ module u2_core
// //////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
- reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
- always @(negedge dsp_clk) pps_negedge <= pps_in;
- always @(posedge dsp_clk) pps_posedge <= pps_in;
- always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
- always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;
+ // No longer used, see time_64bit. Still need to handle mimo time, though
+ assign sc_ack = 0;
- wire pps_o;
- time_sync time_sync
- (.wb_clk_i(wb_clk),.rst_i(wb_rst),
- .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
- .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
- .sys_clk_i(dsp_clk),.master_time_o(master_time),
- .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
- .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
- .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
-
// /////////////////////////////////////////////////////////////////////////
// SD Card Reader / Writer, Slave #13
@@ -644,7 +644,7 @@ module u2_core
// ///////////////////////////////////////////////////////////////////////////////////
// SERDES
-/*
+
serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
(.clk(dsp_clk),.rst(dsp_rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
@@ -654,7 +654,7 @@ module u2_core
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
-*/
+
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
@@ -693,7 +693,7 @@ module u2_core
time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
(.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
- .pps(pps_o), .vita_time(vita_time), .pps_int());
+ .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index d27469f47..1fd8638d9 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -190,8 +190,7 @@ timing/time_64bit.v \
timing/time_compare.v \
timing/time_receiver.v \
timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
+timing/simple_timer.v \
top/u2_core/u2_core.v \
top/u2_rev3/u2_rev3.ucf \
top/u2_rev3/u2_rev3.v
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index 6776e26e5..bffc64e52 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -29,10 +29,13 @@ module vita_tx_control
wire sob = sample_fifo_i[66];
wire send_at = sample_fifo_i[67];
wire now, early, late, too_early;
-
+
+ // FIXME ignore too_early for now for timing reasons
+ assign too_early = 0;
time_compare
time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early),
- .late(late), .too_early(too_early));
+ .late(late), .too_early());
+// .late(late), .too_early(too_early));
localparam IBS_IDLE = 0;
localparam IBS_RUN = 1; // FIXME do we need this?
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 14:33:23 +0000