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-rw-r--r--usrp2/gpmc/dbsm.v88
-rw-r--r--usrp2/gpmc/gpmc.v45
-rw-r--r--usrp2/models/gpmc_model.v23
-rw-r--r--usrp2/top/u1e/tb_u1e.v11
-rw-r--r--usrp2/top/u1e/u1e.v3
-rw-r--r--usrp2/top/u1e/u1e_core.v20
6 files changed, 165 insertions, 25 deletions
diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v
new file mode 100644
index 000000000..0f27be46a
--- /dev/null
+++ b/usrp2/gpmc/dbsm.v
@@ -0,0 +1,88 @@
+
+module bsm
+ (input clk, input reset, input clear,
+ input write_done,
+ input read_done,
+ output readable,
+ output writeable);
+
+ reg state;
+ localparam ST_WRITEABLE = 0;
+ localparam ST_READABLE = 1;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= ST_WRITEABLE;
+ else
+ case(state)
+ ST_WRITEABLE :
+ if(write_done)
+ state <= ST_READABLE;
+ ST_READABLE :
+ if(read_done)
+ state <= ST_WRITEABLE;
+ endcase // case (state)
+
+ assign readable = (state == ST_READABLE);
+ assign writeable = (state == ST_WRITEABLE);
+
+endmodule // bsm
+
+module dbsm
+ (input clk, input reset, input clear,
+ output reg read_sel, output read_ready, input read_done,
+ output reg write_sel, output write_ready, input write_done);
+
+ localparam NUM_BUFS = 2;
+
+ wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf;
+
+ // Two of these buffer state machines
+ genvar i;
+ for(i=0;i<NUM_BUFS;i=i+1)
+ generate
+ bsm bsm(.clk(clk), .reset(reset), .clear(clear),
+ .write_done((write_sel == i) & write_done),
+ .read_done((read_sel == i) & read_done),
+ .readable(readable[i]), .writeable(writeable[i]));
+ endgenerate
+
+ reg full;
+
+ always @(posedge clk)
+ if(reset | clear)
+ begin
+ write_sel <= 0;
+ full <= 0;
+ end
+ else
+ if(write_done)
+ if(writeable[write_sel]==(NUM_BUFS-1))
+ begin
+ write_sel <= 0;
+ if(read_sel == 0)
+ full <= 1;
+ end
+ else
+ begin
+ write_sel <= write_sel + 1;
+ if(read_sel == write_sel + 1)
+ full <= 1;
+ end // else: !if(writeable[write_sel]==(NUM_BUFS-1))
+ else if(read_done)
+ full <= 0;
+
+ always @(posedge clk)
+ if(reset | clear)
+ read_sel <= 0;
+ else
+ if(read_done)
+ if(readable[read_sel]==(NUM_BUFS-1))
+ read_sel <= 0;
+ else
+ read_sel <= read_sel + 1;
+
+ assign write_ready = writeable[write_sel];
+ assign read_ready = readable[read_sel];
+
+endmodule // dbsm
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 88f6809f8..91d02bfec 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -1,4 +1,3 @@
-`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module gpmc
@@ -6,6 +5,9 @@ module gpmc
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+ // GPIOs for FIFO signalling
+ output rx_have_data, output tx_have_space,
+
// Wishbone signals
input wb_clk, input wb_rst,
output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
@@ -13,8 +15,8 @@ module gpmc
// RAM Interface signals
input ram_clk,
- input read_en, input read_sel, input [8:0] read_addr, output [31:0] read_data, output read_rdy,
- input write_en, input write_sel, input [8:0] write_addr, input [31:0] write_data, output write_rdy
+ input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done,
+ input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done
);
wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
@@ -25,14 +27,35 @@ module gpmc
// CS4 is RAM_2PORT for high-speed data
// Writes go into one RAM, reads come from the other
+
+
+ // ////////////////////////////////////////////
+ // Write path
+ wire read_sel_in, write_sel_in, clear_in;
+ wire write_done_in = ~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF);
+
+ ram_2port_mixed_width buffer_in
+ (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(),
+ .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel_in,read_addr}), .di32(0), .do32(read_data));
+
+ dbsm dbsm_in(.clk(wb_clk), .reset(wb_rst), .clear(clear_in),
+ .read_sel(read_sel_in), .read_ready(read_ready), .read_done(read_done),
+ .write_sel(write_sel_in), .write_ready(tx_have_space), .write_done(write_done_in));
+
+
+
+ // ////////////////////////////////////////////
+ // Read path
+ wire read_sel_out, write_sel_out, clear_out;
+ wire read_done_out = ~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF);
- ram_2port_mixed_width buffer_from_host
- (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({store_pg,EM_A}), .di16(EM_D), .do16(),
- .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel,read_addr}), .di32(0), .do32(read_data));
+ ram_2port_mixed_width buffer_out
+ (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram),
+ .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_out,write_addr}), .di32(write_data), .do32());
- ram_2port_mixed_width buffer_to_host
- (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({retr_page,EM_A}), .di16(0), .do16(EM_D_ram),
- .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel,write_addr}), .di32(write_data), .do32());
+ dbsm dbsm_out(.clk(wb_clk), .reset(wb_rst), .clear(clear_out),
+ .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out),
+ .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done));
// CS6 is Control, Wishbone bus bridge (wb master)
// Sync version
@@ -67,13 +90,13 @@ module gpmc
assign wb_cyc_o = wb_stb_o;
always @(posedge wb_clk)
- if( ~cs_del[0] & (we_del == 2'b10) )
+ if(~cs_del[0] & (we_del == 2'b10) )
wb_we_o <= 1;
else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others...
wb_we_o <= 0;
always @(posedge wb_clk)
- if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+ if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
wb_stb_o <= 1;
else if(wb_ack_i)
wb_stb_o <= 0;
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
index 38dde1fa5..1e7dcdde5 100644
--- a/usrp2/models/gpmc_model.v
+++ b/usrp2/models/gpmc_model.v
@@ -22,6 +22,7 @@ module gpmc_model
end
task GPMC_Write;
+ input ctrl;
input [10:0] addr;
input [15:0] data;
begin
@@ -29,10 +30,14 @@ module gpmc_model
EM_A <= addr[10:1];
EM_D_int <= data;
#2.01;
- EM_NCS6 <= 0;
+ if(ctrl)
+ EM_NCS6 <= 0;
+ else
+ EM_NCS4 <= 0;
#14;
EM_NWE <= 0;
#77.5;
+ EM_NCS4 <= 1;
EM_NCS6 <= 1;
//#1.5;
EM_NWE <= 1;
@@ -43,15 +48,20 @@ module gpmc_model
endtask // GPMC_Write
task GPMC_Read;
+ input ctrl;
input [10:0] addr;
begin
#1.3;
EM_A <= addr[10:1];
#3;
- EM_NCS6 <= 0;
+ if(ctrl)
+ EM_NCS6 <= 0;
+ else
+ EM_NCS4 <= 0;
#14;
EM_NOE <= 0;
#77.5;
+ EM_NCS4 <= 1;
EM_NCS6 <= 1;
//#1.5;
$display("Data Read from GPMC: %X",EM_D);
@@ -64,9 +74,14 @@ module gpmc_model
initial
begin
#1000;
- GPMC_Write(36,16'hBEEF);
+ GPMC_Write(1,36,16'hF00D);
#1000;
- GPMC_Read(36);
+ GPMC_Read(1,36);
+ #1000;
+ GPMC_Write(0,36,16'hF00D);
+ GPMC_Write(0,38,16'hF00D);
+ GPMC_Write(0,40,16'hF00D);
+ GPMC_Write(0,11'h7FFE,16'hF00D);
#1000;
$finish;
end
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 319645af6..3cae74c8a 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ps / 1ps
//////////////////////////////////////////////////////////////////////////////////
module tb_u1e();
@@ -20,10 +20,15 @@ module tb_u1e();
wire [10:1] EM_A;
wire [1:0] EM_NBE;
- reg clk_fpga = 0;
+ reg clk_fpga = 0, rst_fpga = 1;
always #15.625 clk_fpga = ~clk_fpga;
+
+ initial #200
+ @(posedge clk_fpga)
+ rst_fpga <= 0;
- u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga),
+ .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
.EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 667372434..066d02ca4 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -21,7 +21,8 @@ module u1e
IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
- u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]),
+ .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
.debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 12c566b6c..7feafeda8 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,8 +1,7 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
module u1e_core
- (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+ (input clk_fpga, input rst_fpga,
+ output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd,
// GPMC
@@ -14,7 +13,8 @@ module u1e_core
inout [15:0] io_tx, inout [15:0] io_rx
);
- wire wb_clk, wb_rst;
+ wire wb_clk = clk_fpga;
+ wire wb_rst = rst_fpga;
// /////////////////////////////////////////////////////////////////////////////////////
// GPMC Slave to Wishbone Master
@@ -31,10 +31,18 @@ module u1e_core
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
.EM_NOE(EM_NOE),
+ .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+
.wb_clk(wb_clk), .wb_rst(wb_rst),
.wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
.wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
- .wb_ack_i(m0_ack));
+ .wb_ack_i(m0_ack),
+
+ .ram_clk(wb_clk),
+ .read_en(read_en), .read_addr(read_addr), .read_data(read_data),
+ .read_ready(read_ready), .read_done(read_done),
+ .write_en(write_en), .write_addr(write_addr), .write_data(write_data),
+ .write_ready(write_ready), .write_done(write_done) );
assign wb_clk = clk_fpga;
@@ -130,7 +138,7 @@ module u1e_core
16'hBEEF;
assign s0_ack = s0_stb & s0_cyc;
- assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios;
+ assign { rx_overrun, tx_underrun } = reg_gpios;
// /////////////////////////////////////////////////////////////////////////////////////
// Slave 1, UART
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 11:00:21 +0000