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-rw-r--r--usrp2/vrt/vita_rx_chain.v10
-rw-r--r--usrp2/vrt/vita_tx_chain.v2
2 files changed, 9 insertions, 3 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index 13defdbc6..150da31c9 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -21,7 +21,7 @@ module vita_rx_chain
parameter UNIT=0,
parameter FIFOSIZE=10,
parameter PROT_ENG_FLAGS=1)
- (input clk, input reset, input clear,
+ (input clk, input reset,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [63:0] vita_time,
input [31:0] sample, input strobe,
@@ -35,7 +35,13 @@ module vita_rx_chain
wire [35:0] rx_data_int;
wire rx_src_rdy_int, rx_dst_rdy_int;
-
+
+ wire clear;
+
+ setting_reg #(.my_addr(BASE+3)) sr
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(),.changed(clear));
+
vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 1db16de63..07e143f19 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -30,6 +30,7 @@ module vita_tx_chain
output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
output [31:0] sample, input strobe,
output underrun, output run,
+ output clear_vita,
output [31:0] debug);
localparam MAXCHAN = 1;
@@ -37,7 +38,6 @@ module vita_tx_chain
wire [FIFOWIDTH-1:0] tx1_data;
wire tx1_src_rdy, tx1_dst_rdy;
- wire clear_vita;
wire [31:0] streamid, message;
wire trigger, sent;
wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;