diff options
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/gen_context_pkt.v | 18 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 2 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_deframer.v | 10 |
3 files changed, 16 insertions, 14 deletions
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 31c2a53e1..0eb035f3e 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -7,8 +7,8 @@ module gen_context_pkt input [31:0] streamid, input [63:0] vita_time, input [31:0] message, - input [15:0] seqnum0, - input [15:0] seqnum1, + input [31:0] seqnum0, + input [31:0] seqnum1, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -19,8 +19,9 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_FLOWCTRL = 8; - localparam CTXT_DONE = 9; + localparam CTXT_FLOWCTRL0 = 8; + localparam CTXT_FLOWCTRL1 = 9; + localparam CTXT_DONE = 10; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -35,7 +36,7 @@ module gen_context_pkt else if(trigger) stored_message <= message; - else if(ctxt_state == CTXT_FLOWCTRL) + else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; always @(posedge clk) @@ -70,14 +71,15 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b00, message }; - CTXT_FLOWCTRL : data_int <= { 2'b10, {seqnum1,seqnum0} }; + CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 }; + CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 09da377f8..eee19bebf 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -29,7 +29,7 @@ module vita_tx_chain wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; - wire [15:0] current_seqnum; + wire [31:0] current_seqnum; assign underrun = error; assign message = error_code; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index d8575b745..40867cc55 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -15,7 +15,7 @@ module vita_tx_deframer output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, - output [15:0] current_seqnum, + output [31:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -48,9 +48,9 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - wire [15:0] seqnum = data_i[15:0]; - reg [15:0] seqnum_reg; - wire [15:0] next_seqnum = seqnum_reg + 16'd1; + wire [31:0] seqnum = data_i; + reg [31:0] seqnum_reg; + wire [31:0] next_seqnum = seqnum_reg + 32'd1; wire [3:0] vita_seqnum = data_i[19:16]; reg [3:0] vita_seqnum_reg; wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; @@ -80,7 +80,7 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear_seqnum) begin - seqnum_reg <= 16'hFFFF; + seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; end else |