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-rw-r--r--usrp2/vrt/gen_context_pkt.v4
-rw-r--r--usrp2/vrt/vita_tx_chain.v50
-rw-r--r--usrp2/vrt/vita_tx_deframer.v11
3 files changed, 41 insertions, 24 deletions
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v
index 0ea2797ec..31c2a53e1 100644
--- a/usrp2/vrt/gen_context_pkt.v
+++ b/usrp2/vrt/gen_context_pkt.v
@@ -3,7 +3,7 @@
module gen_context_pkt
#(parameter PROT_ENG_FLAGS=1)
(input clk, input reset, input clear,
- input trigger, input error, output sent,
+ input trigger, output sent,
input [31:0] streamid,
input [63:0] vita_time,
input [31:0] message,
@@ -33,7 +33,7 @@ module gen_context_pkt
if(reset | clear)
stored_message <= 0;
else
- if(error)
+ if(trigger)
stored_message <= message;
else if(ctxt_state == CTXT_FLOWCTRL)
stored_message <= 0;
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 12e94b1a8..09da377f8 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -3,7 +3,9 @@ module vita_tx_chain
#(parameter BASE_CTRL=0,
parameter BASE_DSP=0,
parameter REPORT_ERROR=0,
- parameter PROT_ENG_FLAGS=0)
+ parameter DO_FLOW_CONTROL=0,
+ parameter PROT_ENG_FLAGS=0,
+ parameter USE_TRANS_HEADER=0)
(input clk, input reset,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [63:0] vita_time,
@@ -36,7 +38,10 @@ module vita_tx_chain
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(streamid),.changed(clear_seqnum));
- vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer
+ vita_tx_deframer #(.BASE(BASE_CTRL),
+ .MAXCHAN(MAXCHAN),
+ .USE_TRANS_HEADER(USE_TRANS_HEADER))
+ vita_tx_deframer
(.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
@@ -59,23 +64,34 @@ module vita_tx_chain
.dac_a(dac_a),.dac_b(dac_b),
.debug(debug_tx_dsp) );
- generate
- if(REPORT_ERROR==1)
- begin
- gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
- (.clk(clk), .reset(reset), .clear(clear_vita),
- .trigger(trigger),.error(error), .sent(),
- .streamid(streamid), .vita_time(vita_time), .message(message),
- .seqnum0(current_seqnum), .seqnum1(16'd0),
- .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
- trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt
- (.clk(clk), .reset(reset), .clear(clear_vita),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .packet_consumed(packet_consumed), .trigger(trigger));
- end
- endgenerate
+ wire [35:0] flow_data, err_data_int;
+ wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int;
+
+ gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(),
+ .streamid(streamid), .vita_time(vita_time), .message(32'd0),
+ .seqnum0(current_seqnum), .seqnum1(16'd0),
+ .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy));
+ trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .packet_consumed(packet_consumed), .trigger(trigger));
+
+ gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .trigger(error & (REPORT_ERROR==1)), .sent(),
+ .streamid(streamid), .vita_time(vita_time), .message(message),
+ .seqnum0(current_seqnum), .seqnum1(16'd0),
+ .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int));
//assign debug = debug_vtc | debug_vtd;
assign debug = { debug_vtd[15:0], current_seqnum };
+ fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int),
+ .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy),
+ .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
+
endmodule // vita_tx_chain
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index e12747cd5..c55f43373 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -1,7 +1,8 @@
module vita_tx_deframer
#(parameter BASE=0,
- parameter MAXCHAN=1)
+ parameter MAXCHAN=1,
+ parameter USE_TRANS_HEADER=0)
(input clk, input reset, input clear, input clear_seqnum,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -93,7 +94,7 @@ module vita_tx_deframer
always @(posedge clk)
if(reset | clear)
begin
- vita_state <= VITA_TRANS_HEADER;
+ vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER;
{has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg}
<= 0;
seqnum_err <= 0;
@@ -104,7 +105,7 @@ module vita_tx_deframer
if(has_trailer_reg)
vita_state <= VITA_TRAILER;
else
- vita_state <= VITA_TRANS_HEADER;
+ vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER;
else
begin
vita_state <= VITA_PAYLOAD;
@@ -171,11 +172,11 @@ module vita_tx_deframer
else
vector_phase <= vector_phase + 1;
VITA_TRAILER :
- vita_state <= VITA_TRANS_HEADER;
+ vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER;
VITA_STORE :
;
default :
- vita_state <= VITA_TRANS_HEADER;
+ vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER;
endcase // case (vita_state)
assign line_done = (vector_phase == numchan);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 03:45:42 +0000