diff options
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/gen_context_pkt.v | 7 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 8 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_control.v | 9 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_deframer.v | 2 |
4 files changed, 13 insertions, 13 deletions
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 0eb035f3e..efc170743 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -38,9 +38,10 @@ module gen_context_pkt stored_message <= message; else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; - + + // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe always @(posedge clk) - if(reset | clear) + if(reset) begin ctxt_state <= CTXT_IDLE; seqno <= 0; @@ -84,7 +85,7 @@ module gen_context_pkt endcase // case (ctxt_state) fifo_short #(.WIDTH(34)) ctxt_fifo - (.clk(clk), .reset(reset), .clear(clear), + (.clk(clk), .reset(reset), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); assign data_o[35:34] = 2'b00; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 00da4c6e1..21e826f1c 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -33,7 +33,11 @@ module vita_tx_chain assign underrun = error & ~(error_code == 1); assign message = error_code; - + + setting_reg #(.my_addr(BASE_CTRL+1)) sr + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_vita)); + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); @@ -88,7 +92,7 @@ module vita_tx_chain assign debug = debug_vtc | debug_vtd; fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages - (.clk(clk), .reset(reset), .clear(clear_vita), + (.clk(clk), .reset(reset), .clear(0), // Don't clear this or it could get clogged .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 936762212..eb41c54c0 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -58,11 +58,6 @@ module vita_tx_control reg [2:0] ibs_state; - wire clear_state; - setting_reg #(.my_addr(BASE+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_state)); - wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -74,7 +69,7 @@ module vita_tx_control reg send_error; always @(posedge clk) - if(reset | clear_state) + if(reset | clear) begin ibs_state <= IBS_IDLE; send_error <= 0; @@ -163,7 +158,7 @@ module vita_tx_control assign error = send_error; always @(posedge clk) - if(reset) + if(reset | clear) packet_consumed <= 0; else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 7fb8e3893..7697be367 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -80,7 +80,7 @@ module vita_tx_deframer wire fifo_space; always @(posedge clk) - if(reset | clear_seqnum) + if(reset | clear | clear_seqnum) begin seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; |