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-rw-r--r--usrp2/vrt/vita_rx_control.v39
-rw-r--r--usrp2/vrt/vita_rx_framer.v25
-rw-r--r--usrp2/vrt/vita_rx_tb.v67
3 files changed, 76 insertions, 55 deletions
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index ba63181f1..0769f3a24 100644
--- a/usrp2/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
@@ -9,7 +9,7 @@ module vita_rx_control
output overrun,
// To vita_rx_framer
- output [4+64+WIDTH-1:0] sample_fifo_o,
+ output [5+64+WIDTH-1:0] sample_fifo_o,
output sample_fifo_src_rdy_o,
input sample_fifo_dst_rdy_i,
@@ -32,7 +32,7 @@ module vita_rx_control
wire [28:0] numlines_pre;
wire send_imm_pre, chain_pre, reload_pre;
reg send_imm, chain, reload;
- wire read_ctrl, empty_ctrl, write_ctrl;
+ wire read_ctrl, not_empty_ctrl, write_ctrl;
reg sc_pre2;
wire [33:0] fifo_line;
reg [28:0] lines_left, lines_total;
@@ -62,12 +62,12 @@ module vita_rx_control
assign write_ctrl = sc_pre1 & ~sc_pre2;
wire [4:0] command_queue_len;
-
+
fifo_short #(.WIDTH(96)) commandfifo
(.clk(clk),.reset(reset),.clear(clear),
.datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(),
.dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
- .src_rdy_o(empty_ctrl), .dst_rdy_i(read_ctrl),
+ .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl),
.occupied(command_queue_len), .space() );
reg [33:0] pkt_fifo_line;
@@ -78,19 +78,22 @@ module vita_rx_control
localparam IBS_OVERRUN = 4;
localparam IBS_BROKENCHAIN = 5;
localparam IBS_LATECMD = 6;
-
- wire signal_cmd_done = (lines_left == 1) & (~chain | (~empty_ctrl & (numlines_pre==0)));
+ localparam IBS_ZEROLEN = 7;
+
+ wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0)));
wire signal_overrun = (ibs_state == IBS_OVERRUN);
wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN);
wire signal_latecmd = (ibs_state == IBS_LATECMD);
+ wire signal_zerolen = (ibs_state == IBS_ZEROLEN);
// Buffer of samples for while we're writing the packet headers
- wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+ wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
wire attempt_sample_write = ((run & strobe) | (ibs_state==IBS_OVERRUN) |
- (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD));
+ (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) |
+ (ibs_state==IBS_ZEROLEN));
- fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
+ fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy),
.dataout(sample_fifo_o),
@@ -119,12 +122,15 @@ module vita_rx_control
else
case(ibs_state)
IBS_IDLE :
- if(~empty_ctrl)
+ if(not_empty_ctrl)
begin
lines_left <= numlines_pre;
lines_total <= numlines_pre;
rcvtime <= rcvtime_pre;
- ibs_state <= IBS_WAITING;
+ if(numlines_pre == 0)
+ ibs_state <= IBS_ZEROLEN;
+ else
+ ibs_state <= IBS_WAITING;
send_imm <= send_imm_pre;
chain <= chain_pre;
reload <= reload_pre;
@@ -144,12 +150,12 @@ module vita_rx_control
if(lines_left == 1)
if(~chain)
ibs_state <= IBS_IDLE;
- else if(empty_ctrl & reload)
+ else if(~not_empty_ctrl & reload)
begin
ibs_state <= IBS_RUNNING;
lines_left <= lines_total;
end
- else if(empty_ctrl)
+ else if(~not_empty_ctrl)
ibs_state <= IBS_BROKENCHAIN;
else
begin
@@ -174,17 +180,20 @@ module vita_rx_control
IBS_BROKENCHAIN :
if(sample_fifo_in_rdy)
ibs_state <= IBS_IDLE;
+ IBS_ZEROLEN :
+ if(sample_fifo_in_rdy)
+ ibs_state <= IBS_IDLE;
endcase // case(ibs_state)
assign overrun = (ibs_state == IBS_OVERRUN);
assign run = (ibs_state == IBS_RUNNING);
assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
- & ~empty_ctrl;
+ & not_empty_ctrl;
assign debug_rx = { { ibs_state[2:0], command_queue_len },
{ 8'd0 },
- { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, empty_ctrl },
+ { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl },
{ 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
endmodule // rx_control
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index 1065ce637..bce8fe334 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -11,7 +11,7 @@ module vita_rx_framer
output src_rdy_o,
// From vita_rx_control
- input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i,
+ input [5+64+(32*MAXCHAN)-1:0] sample_fifo_i,
input sample_fifo_src_rdy_i,
output sample_fifo_dst_rdy_o,
@@ -23,11 +23,11 @@ module vita_rx_framer
output [31:0] debug_rx
);
- localparam SAMP_WIDTH = 4+64+(32*MAXCHAN);
+ localparam SAMP_WIDTH = 5+64+(32*MAXCHAN);
reg [3:0] sample_phase;
wire [3:0] numchan;
- wire [3:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4];
- wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68];
+ wire [4:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-5];
+ wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-6:SAMP_WIDTH-69];
reg [31:0] data_fifo_o;
@@ -55,7 +55,7 @@ module vita_rx_framer
reg [3:0] pkt_count;
wire [15:0] vita_pkt_len = samples_per_packet + 6;
- //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+ //wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
setting_reg #(.my_addr(BASE+4)) sr_header
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
@@ -69,11 +69,11 @@ module vita_rx_framer
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(vita_trailer),.changed());
- setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt
+ setting_reg #(.my_addr(BASE+7),.width(16)) sr_samples_per_pkt
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(samples_per_packet),.changed());
- setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan
+ setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
@@ -107,7 +107,8 @@ module vita_rx_framer
always @*
case(vita_state)
// Data packets are IF Data packets with or w/o streamid, no classid, with trailer
- VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len};
+ VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24],
+ vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]};
VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
@@ -121,7 +122,7 @@ module vita_rx_framer
VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
- VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o};
//VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
@@ -140,7 +141,7 @@ module vita_rx_framer
sample_ctr <= 1;
sample_phase <= 0;
if(sample_fifo_src_rdy_i)
- if(|flags_fifo_o[3:1])
+ if(|flags_fifo_o[4:1])
vita_state <= VITA_ERR_HEADER;
else
vita_state <= VITA_HEADER;
@@ -185,7 +186,7 @@ module vita_rx_framer
req_write_pkt_fifo <= 1;
VITA_PAYLOAD :
// Write if sample ready and no error flags
- req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
+ req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]);
VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
req_write_pkt_fifo <= 1;
default :
@@ -205,7 +206,7 @@ module vita_rx_framer
assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
( ((vita_state==VITA_PAYLOAD) &
(sample_phase == (numchan-4'd1)) &
- ~|flags_fifo_o[3:1]) |
+ ~|flags_fifo_o[4:1]) |
(vita_state==VITA_ERR_PAYLOAD));
assign debug_rx = vita_state;
diff --git a/usrp2/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v
index 3e01e2ee2..023934f39 100644
--- a/usrp2/vrt/vita_rx_tb.v
+++ b/usrp2/vrt/vita_rx_tb.v
@@ -37,7 +37,7 @@ module vita_rx_tb;
wire sample_dst_rdy, sample_src_rdy;
//wire [99:0] sample_data_o;
- wire [64+4+(MAXCHAN*32)-1:0] sample_data_o;
+ wire [64+5+(MAXCHAN*32)-1:0] sample_data_o;
vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
(.clk(clk), .reset(reset), .clear(0),
@@ -92,58 +92,68 @@ module vita_rx_tb;
begin
@(negedge reset);
@(posedge clk);
- write_setting(4,32'hDEADBEEF); // VITA header
+ write_setting(4,32'h15F00000); // VITA header
write_setting(5,32'hF00D1234); // VITA streamid
- write_setting(6,32'hF0000000); // VITA trailer
+ write_setting(6,32'hE0000000); // VITA trailer
write_setting(7,8); // Samples per VITA packet
- write_setting(8,NUMCHAN); // Samples per VITA packet
- queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
- queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth
- queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth
- queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet
+ write_setting(8,NUMCHAN); // Vector length
+
+ queue_rx_cmd(1,1,0,10,32'h0,32'h0); // send imm, single packet
+ #10000;
+
+ queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet
+ //queue_rx_cmd(1,1,0,0,32'h0,32'h0); // send imm, single packet
+
+ //queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet
+
+ /*
+ queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet
+ queue_rx_cmd(1,0,0,16,32'h0,32'h0); // send imm, 2 packets worth
+ queue_rx_cmd(1,0,0,7,32'h0,32'h0); // send imm, 1 short packet worth
+ queue_rx_cmd(1,0,0,9,32'h0,32'h0); // send imm, just longer than 1 packet
- queue_rx_cmd(1,1,16,32'h0,32'h0); // chained
- queue_rx_cmd(0,0,8,32'h0,32'h0); // 2nd in chain
+ queue_rx_cmd(1,1,0,16,32'h0,32'h0); // chained
+ queue_rx_cmd(0,0,0,8,32'h0,32'h0); // 2nd in chain
- queue_rx_cmd(1,1,17,32'h0,32'h0); // chained, odd length
- queue_rx_cmd(0,0,9,32'h0,32'h0); // 2nd in chain, also odd length
+ queue_rx_cmd(1,1,0,17,32'h0,32'h0); // chained, odd length
+ queue_rx_cmd(0,0,0,9,32'h0,32'h0); // 2nd in chain, also odd length
- queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time
- queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late
+ queue_rx_cmd(0,0,0,8,32'h0,32'h340); // send at, on time
+ queue_rx_cmd(0,0,0,8,32'h0,32'h100); // send at, but late
#100000;
$display("\nChained, break chain\n");
- queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain
+ queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained, but break chain
#100000;
$display("\nSingle packet\n");
- queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
+ queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet
#100000;
$display("\nEnd chain with zero samples, shouldn't error\n");
- queue_rx_cmd(1,1,8,32'h0,32'h0); // chained
- queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
+ queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained
+ queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
#100000;
$display("\nEnd chain with zero samples on odd-length, shouldn't error\n");
- queue_rx_cmd(1,1,14,32'h0,32'h0); // chained
- queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
+ queue_rx_cmd(1,1,0,14,32'h0,32'h0); // chained
+ queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
#100000;
$display("Should have gotten 14 samples and EOF by now\n");
- queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd length
+ queue_rx_cmd(1,1,0,9,32'h0,32'h0); // chained, but break chain, odd length
#100000;
dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun
- queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos
- queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent
+ queue_rx_cmd(1,0,0,100,32'h0,32'h0); // long enough to fill the fifos
+ queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent
#100000;
dst_rdy <= 1; // restart the reads so we can see what we got
#100000;
dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun
- queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos
- //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent
+ queue_rx_cmd(1,1,0,100,32'h0,32'h0); // long enough to fill the fifos
+ //queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent
#100000;
@(posedge clk);
dst_rdy <= 1;
-
+ */
#100000 $finish;
end
@@ -164,11 +174,12 @@ module vita_rx_tb;
task queue_rx_cmd;
input send_imm;
input chain;
- input [29:0] lines;
+ input reload;
+ input [28:0] lines;
input [31:0] secs;
input [31:0] tics;
begin
- write_setting(0,{send_imm,chain,lines});
+ write_setting(0,{send_imm,chain,reload,lines});
write_setting(1,secs);
write_setting(2,tics);
end
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 08:32:50 +0000