diff options
Diffstat (limited to 'usrp2/vrt/vita_tx_chain.v')
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 33 |
1 files changed, 21 insertions, 12 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 84e502b5f..ad9f11fc6 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -12,30 +12,39 @@ module vita_tx_chain output [15:0] dac_a, output [15:0] dac_b, output underrun, output run, output [31:0] debug); + + localparam MAXCHAN = 1; + localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + + wire [FIFOWIDTH-1:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire clear_vita; + wire [31:0] sample_tx; + wire [31:0] streamid, message; + wire trigger, sent; + wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; + + wire error; + wire [3:0] error_code; - wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire [99:0] tx1_data; - wire tx1_src_rdy, tx1_dst_rdy; - wire clear_vita; - wire [31:0] sample_tx; - wire [31:0] streamid, message; - wire trigger, sent; - + assign underrun = error; + assign message = {28'h0,error_code}; + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed()); - vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(1)) vita_tx_deframer + vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), .debug(debug_vtd) ); - vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32)) vita_tx_control + vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(underrun), + .vita_time(vita_time),.error(error),.error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run), .strobe(strobe_tx), .debug(debug_vtc) ); @@ -51,7 +60,7 @@ module vita_tx_chain if(REPORT_ERROR==1) gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(underrun), .sent(), + .trigger(error), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); endgenerate |