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-rwxr-xr-xusrp2/vrt/vita_rx.build1
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diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build
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+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v