diff options
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 4 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 4 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 4 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 21 |
4 files changed, 21 insertions, 12 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index c883c5ca8..0a03517b6 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -155,7 +155,7 @@ module u1plus_core wire [35:0] vita_rx_data0; wire vita_rx_src_rdy0, vita_rx_dst_rdy0; - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), @@ -178,7 +178,7 @@ module u1plus_core wire [35:0] vita_rx_data1; wire vita_rx_src_rdy1, vita_rx_dst_rdy1; - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index aede63bac..b581ed50a 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -160,7 +160,7 @@ module u1e_core wire [35:0] vita_rx_data0; wire vita_rx_src_rdy0, vita_rx_dst_rdy0; - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), @@ -183,7 +183,7 @@ module u1e_core wire [35:0] vita_rx_data1; wire vita_rx_src_rdy1, vita_rx_dst_rdy1; - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 3ead0db8e..f78d9013f 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -576,7 +576,7 @@ module u2plus_core always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), @@ -604,7 +604,7 @@ module u2plus_core always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index bbd0e9337..da12371bb 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -564,10 +564,10 @@ module u2_core always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), + .adc_i(adc_i),.adc_q(adc_q), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -592,10 +592,10 @@ module u2_core always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), + .adc_i(adc_i),.adc_q(adc_q), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); @@ -648,8 +648,10 @@ module u2_core .debug2(debug_extfifo2) ); wire [23:0] tx_i, tx_q; + wire [31:0] sample_tx; + wire strobe_tx; - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + vita_tx_chain #(.BASE(SR_TX_CTRL), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) @@ -659,10 +661,17 @@ module u2_core .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .tx_i(tx_i),.tx_q(tx_q), + .sample(sample_tx), .strobe(strobe_tx), .underrun(underrun), .run(run_tx), .debug(debug_vt)); + duc_chain #(.BASE(SR_TX_DSP)) duc_chain + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .dac_i(tx_i),.dac_q(tx_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), |