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-rwxr-xr-xusrp2/top/u1plus/core_compile2
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile
new file mode 100755
index 000000000..0d95f704d
--- /dev/null
+++ b/usrp2/top/u1plus/core_compile
@@ -0,0 +1,2 @@
+iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1
+