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-rw-r--r--usrp2/top/u1e/Makefile3
-rw-r--r--usrp2/top/u1e/tb_u1e.v25
-rw-r--r--usrp2/top/u1e/u1e.ucf14
-rw-r--r--usrp2/top/u1e/u1e.v33
-rw-r--r--usrp2/top/u1e/u1e_core.v52
5 files changed, 93 insertions, 34 deletions
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index e9c101226..cdbdf995e 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -174,7 +174,8 @@ timing/time_receiver.v \
timing/time_sender.v \
timing/time_sync.v \
timing/timer.v \
-top/u2_core/u2_core.v \
+gpmc/gpmc.v \
+top/u1e/u1e_core.v \
top/u1e/u1e.ucf \
top/u1e/u1e.v
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..6e0c60e17
--- /dev/null
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+
+ wire [2:0] debug_led;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+
+ // GPMC
+ wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+ wire [15:0] EM_D;
+ wire [10:1] EM_A;
+ wire [1:0] EM_NBE;
+
+ reg clk_fpga = 0;
+ always #100 clk_fpga = ~clk_fpga;
+
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+endmodule // u1e
diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
index cb6d6372e..3b524a6ea 100644
--- a/usrp2/top/u1e/u1e.ucf
+++ b/usrp2/top/u1e/u1e.ucf
@@ -3,8 +3,6 @@ NET "CLK_FPGA_P" LOC = "Y11" ;
NET "CLK_FPGA_N" LOC = "Y10" ;
## GPMC
-NET "EM_CLK" LOC = "F11" ;
-
NET "EM_D<15>" LOC = "D13" ;
NET "EM_D<14>" LOC = "D15" ;
NET "EM_D<13>" LOC = "C16" ;
@@ -33,20 +31,20 @@ NET "EM_A<3>" LOC = "E7" ;
NET "EM_A<2>" LOC = "A7" ;
NET "EM_A<1>" LOC = "C15" ;
-#NET "EM_NCS6" LOC = "E17" ;
+NET "EM_NCS6" LOC = "E17" ;
#NET "EM_NCS5" LOC = "E10" ;
NET "EM_NCS4" LOC = "E6" ;
#NET "EM_NCS1" LOC = "D18" ;
#NET "EM_NCS0" LOC = "D17" ;
+NET "EM_CLK" LOC = "F11" ;
NET "EM_WAIT0" LOC = "F14" ;
-#NET "EM_NBE1" LOC = "D14" ;
-#NET "EM_NBE0" LOC = "A13" ;
-NET "EM_NWP" LOC = "F13" ;
+NET "EM_NBE<1>" LOC = "D14" ;
+NET "EM_NBE<0>" LOC = "A13" ;
NET "EM_NWE" LOC = "B13" ;
NET "EM_NOE" LOC = "A14" ;
-NET "EM_NADV_ALE" LOC = "B15" ;
-
+#NET "EM_NADV_ALE" LOC = "B15" ;
+#NET "EM_NWP" LOC = "F13" ;
## Overo GPIO
#NET "overo_gpio0" LOC = "F9" ;
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index e28a6a582..8832d6e11 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -2,13 +2,12 @@
//////////////////////////////////////////////////////////////////////////////////
module u1e
- (
- input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Diff
output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
// GPMC
- input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A,
- input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE
);
// FPGA-specific pins connections
@@ -17,25 +16,9 @@ module u1e
IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
- // Debug circuitry
- reg [31:0] ctr;
- always @(posedge clk_fpga)
- ctr <= ctr + 1;
-
-
- assign debug_led = ctr[27:25];
- assign debug_clk = { EM_CLK, clk_fpga };
- assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
- { EM_D } };
-
- wire EM_output_enable = (~EM_NOE & ~EM_NCS4);
- wire [15:0] EM_D_out;
-
- assign EM_D = EM_output_enable ? EM_D_out : 16'bz;
-
- ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
- (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out),
- .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
-
-endmodule // u2plus
+endmodule // u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
new file mode 100644
index 000000000..2481549b2
--- /dev/null
+++ b/usrp2/top/u1e/u1e_core.v
@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e_core
+ (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+
+ // GPMC
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE
+ );
+
+ // Debug circuitry
+ reg [31:0] ctr;
+ always @(posedge clk_fpga)
+ ctr <= ctr + 1;
+
+ assign debug_led = ctr[27:25];
+ assign debug_clk = { EM_CLK, clk_fpga };
+ assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ { EM_D } };
+
+ wire wb_clk, wb_rst;
+ wire wb_cyc, wb_stb, wb_we, wb_ack;
+ wire [1:0] wb_sel;
+ wire [10:0] wb_adr;
+ wire [15:0] wb_dat_mosi, wb_dat_miso;
+
+ gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
+ .EM_NOE(EM_NOE),
+
+ .wb_clk(wb_clk), .wb_rst(wb_rst),
+ .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+ .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we),
+ .wb_ack_i(wb_ack));
+
+ assign wb_clk = clk_fpga;
+ reg [15:0] reg_fast, reg_slow;
+
+ localparam [10:0] WB_ADR_REG_FAST = 36;
+ localparam [10:0] WB_ADR_REG_SLOW = 38;
+
+ always @(posedge wb_clk)
+ if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST))
+ reg_fast <= wb_dat_mosi;
+
+ assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx;
+
+ assign wb_ack = wb_stb & wb_cyc;
+
+
+endmodule // u2plus
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 11:29:25 +0000