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-rw-r--r--usrp2/top/E1x0/u1e.v4
-rw-r--r--usrp2/top/E1x0/u1e_core.v4
2 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v
index adf42fd07..92915814c 100644
--- a/usrp2/top/E1x0/u1e.v
+++ b/usrp2/top/E1x0/u1e.v
@@ -75,7 +75,7 @@ module u1e
clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst),
.DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(),
.CLKDV(), .CLKFX(), .CLKFX180(),
- .CLK2X(), .CLK2X180(),
+ .CLK2X(clk_2x), .CLK2X180(),
.CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(),
.LOCKED(dcm_locked), .STATUS());
@@ -130,7 +130,7 @@ module u1e
// /////////////////////////////////////////////////////////////////////////
// Main U1E Core
- u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .bus_clk(clk_2x), .rst_fpga(~debug_pb),
.debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
.debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 4c513587b..00335d118 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -18,7 +18,7 @@
module u1e_core
- (input clk_fpga, input rst_fpga,
+ (input clk_fpga, input bus_clk, input rst_fpga,
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
output debug_txd, input debug_rxd,
@@ -110,7 +110,7 @@ module u1e_core
.in(set_data),.out(),.changed(clear_tx));
gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
- gpmc (.arst(wb_rst),
+ gpmc (.arst(wb_rst), .bus_clk(bus_clk),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
.EM_NOE(EM_NOE),