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-rw-r--r--usrp2/top/Makefile.common2
-rw-r--r--usrp2/top/u1e/u1e_core.v62
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v56
3 files changed, 57 insertions, 63 deletions
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index d0435fa1e..4da64ac28 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -47,7 +47,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST)
@echo $@
$(ISE_HELPER) ""
-$(BIN_FILE): $(ISE_FILE)
+$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
@echo $@
$(ISE_HELPER) "Generate Programming File"
touch $@
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 63488f549..d7c4ff509 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -59,8 +59,9 @@ module u1e_core
wire [31:0] debug_gpmc;
- wire [35:0] tx_data, rx_data;
- wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
+ wire [35:0] tx_data, rx_data, tx_err_data;
+ wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy,
+ tx_err_src_rdy, tx_err_dst_rdy;
reg [15:0] tx_frame_len;
wire [15:0] rx_frame_len;
wire [7:0] rate;
@@ -109,8 +110,7 @@ module u1e_core
assign tx_underrun = 0;
assign rx_overrun = 0;
- wire run_tx, run_rx, strobe_tx, strobe_rx, tx1_src_rdy, tx1_dst_rdy;
- wire [31:0] debug_vtd, debug_vtc;
+ wire run_tx, run_rx, strobe_tx, strobe_rx;
`endif // LOOPBACK
`ifdef TIMED
@@ -154,8 +154,9 @@ module u1e_core
wire rx1_dst_rdy, rx1_src_rdy;
wire [99:0] rx1_data;
wire run_rx;
-
-
+ wire [35:0] vita_rx_data;
+ wire vita_rx_src_rdy, vita_rx_dst_rdy;
+
dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -175,41 +176,35 @@ module u1e_core
(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
- .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy),
+ .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
.fifo_occupied(), .fifo_full(), .fifo_empty(),
.debug_rx(vrf_debug) );
-
+
+ fifo36_mux #(.prio(0)) mux_err_stream
+ (.clk(wb_clk), .reset(wb_rst), .clear(0),
+ .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy),
+ .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+ .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
- wire [99:0] tx1_data;
- wire tx1_src_rdy, tx1_dst_rdy;
wire [15:0] tx_i_int, tx_q_int;
- wire [31:0] debug_vtc, debug_vtd, debug_vt;
+ wire [31:0] debug_vt;
wire run_tx;
- vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
- .debug(debug_vtd) );
-
- vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .vita_time(vita_time),.underrun(tx_underrun),
- .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
- .debug(debug_vtc) );
-
- dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
- (.clk(wb_clk),.rst(wb_rst),
+ vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ .REPORT_ERROR(1), .PROT_ENG_FLAGS(0))
+ vita_tx_chain
+ (.clk(wb_clk), .reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .vita_time(vita_time),
+ .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+ .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(tx_i_int),.dac_b(tx_q_int),
- .debug(debug_tx_dsp) );
-
+ .underrun(underrun), .run(run_tx),
+ .debug(debug_vt));
+
assign tx_i = tx_i_int[15:2];
assign tx_q = tx_q_int[15:2];
@@ -433,14 +428,15 @@ module u1e_core
// Debug circuitry
assign debug_clk = { EM_CLK, clk_fpga };
+
assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun },
{ tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
{ EM_D } };
assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]},
- {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
+ {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
- assign debug_gpio_1 = debug_vtd | debug_vtc;
+ assign debug_gpio_1 = debug_vt;
/*
assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index b034791a7..124930c23 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -423,7 +423,10 @@ module u2_core
cycle_count <= 0;
else
cycle_count <= cycle_count + 1;
-
+
+ //compatibility number -> increment when the fpga has been sufficiently altered
+ localparam compat_num = 32'd1;
+
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
@@ -431,7 +434,7 @@ module u2_core
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
);
// /////////////////////////////////////////////////////////////////////////
@@ -466,11 +469,20 @@ module u2_core
.tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
.debug(debug_udp) );
+ wire [35:0] tx_err_data, udp1_tx_data;
+ wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+ .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+ fifo36_mux #(.prio(0)) mux_err_stream
+ (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
+ .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
+ .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+ .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
@@ -639,40 +651,26 @@ module u2_core
// DSP TX
wire [35:0] tx_data;
- wire [99:0] tx1_data;
- wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
-
- wire [31:0] debug_vtc, debug_vtd, debug_vt;
+ wire tx_src_rdy, tx_dst_rdy;
+ wire [31:0] debug_vt;
fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
- vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
- .debug(debug_vtd) );
-
- vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .vita_time(vita_time),.underrun(underrun),
- .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
- .debug(debug_vtc) );
-
- assign debug_vt = debug_vtc | debug_vtd;
-
- dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
- (.clk(dsp_clk),.rst(dsp_rst),
+ vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ .REPORT_ERROR(1), .PROT_ENG_FLAGS(1))
+ vita_tx_chain
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .vita_time(vita_time),
+ .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+ .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(dac_a),.dac_b(dac_b),
- .debug(debug_tx_dsp) );
-
+ .underrun(underrun), .run(run_tx),
+ .debug(debug_vt));
+
assign dsp_rst = wb_rst;
// ///////////////////////////////////////////////////////////////////////////////////
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-18 07:34:03 +0000