2 files changed, 7 insertions, 4 deletions
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
index 5e4db5c65..291c723b8 100644
--- a/usrp2/top/u1e/cmdfile
+++ b/usrp2/top/u1e/cmdfile
@@ -10,10 +10,11 @@
 
 # Models
 -y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
 
 # Open Cores
--y ../opencores/spi/rtl/verilog
-+incdir+../opencores/spi/rtl/verilog
--y ../opencores/i2c/rtl/verilog
-+incdir+../opencores/i2c/rtl/verilog
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
 
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 85d2b49f0..319645af6 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -7,6 +7,8 @@ module tb_u1e();
    wire [31:0] debug;
    wire [1:0] debug_clk;
 
+   xlnx_glbl glbl (.GSR(),.GTS());
+
    initial begin
       $dumpfile("tb_u1e.lxt");
       $dumpvars(0,tb_u1e);