diff options
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/B100/.gitignore (renamed from usrp2/top/safe_u1plus/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/top/B100/Makefile (renamed from usrp2/top/u1plus/Makefile) | 0 | ||||
| -rwxr-xr-x | usrp2/top/B100/core_compile (renamed from usrp2/top/u1plus/core_compile) | 0 | ||||
| -rw-r--r-- | usrp2/top/B100/timing.ucf (renamed from usrp2/top/u1plus/timing.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus.ucf (renamed from usrp2/top/u1plus/u1plus.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus.v (renamed from usrp2/top/u1plus/u1plus.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v (renamed from usrp2/top/u1plus/u1plus_core.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/.gitignore (renamed from usrp2/top/u1e/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/Makefile (renamed from usrp2/top/u1e/Makefile) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/Makefile.passthru (renamed from usrp2/top/u1e_passthru/Makefile) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/README (renamed from usrp2/top/u1e/README) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/cmdfile (renamed from usrp2/top/u1e/cmdfile) | 0 | ||||
| -rwxr-xr-x | usrp2/top/E1x0/core_compile (renamed from usrp2/top/u1e/core_compile) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/make.sim (renamed from usrp2/top/u1e/make.sim) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/passthru.ucf (renamed from usrp2/top/u1e_passthru/passthru.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/passthru.v (renamed from usrp2/top/u1e_passthru/passthru.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/tb_u1e.v (renamed from usrp2/top/u1e/tb_u1e.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/timing.ucf (renamed from usrp2/top/u1e/timing.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e.ucf (renamed from usrp2/top/u1e/u1e.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e.v (renamed from usrp2/top/u1e/u1e.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v (renamed from usrp2/top/u1e/u1e_core.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/.gitignore (renamed from usrp2/top/u1e_passthru/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N200R3 (renamed from usrp2/top/u2plus/Makefile.N200R3) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N200R4 (renamed from usrp2/top/u2plus/Makefile.N200R4) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R3 (renamed from usrp2/top/u2plus/Makefile.N210R3) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R4 (renamed from usrp2/top/u2plus/Makefile.N210R4) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/bootloader.rmi (renamed from usrp2/top/u2plus/bootloader.rmi) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/capture_ddrlvds.v (renamed from usrp2/top/u2plus/capture_ddrlvds.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/rev4_defs.v (renamed from usrp2/top/u2plus/rev4_defs.v) | 0 | ||||
| -rwxr-xr-x | usrp2/top/N2x0/u2plus.ucf (renamed from usrp2/top/u2plus/u2plus.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus.v (renamed from usrp2/top/u2plus/u2plus.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v (renamed from usrp2/top/u2plus/u2plus_core.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/USRP2/.gitignore (renamed from usrp2/top/u2_rev3/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/top/USRP2/Makefile (renamed from usrp2/top/u2_rev3/Makefile) | 0 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v (renamed from usrp2/top/u2_rev3/u2_core.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_rev3.ucf (renamed from usrp2/top/u2_rev3/u2_rev3.ucf) | 0 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_rev3.v (renamed from usrp2/top/u2_rev3/u2_rev3.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/Makefile | 122 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.ucf | 171 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.v | 28 | ||||
| -rw-r--r-- | usrp2/top/safe_u2plus/.gitignore | 2 | ||||
| -rw-r--r-- | usrp2/top/safe_u2plus/Makefile | 245 | ||||
| -rw-r--r-- | usrp2/top/safe_u2plus/safe_u2plus.v | 23 | ||||
| -rwxr-xr-x | usrp2/top/safe_u2plus/u2plus.ucf | 401 | ||||
| -rw-r--r-- | usrp2/top/single_u2_sim/single_u2_sim.v | 324 | ||||
| -rw-r--r-- | usrp2/top/u1plus/.gitignore | 1 | ||||
| -rw-r--r-- | usrp2/top/u2plus/.gitignore | 1 |
47 files changed, 0 insertions, 1318 deletions
diff --git a/usrp2/top/safe_u1plus/.gitignore b/usrp2/top/B100/.gitignore index 1b2211df0..1b2211df0 100644 --- a/usrp2/top/safe_u1plus/.gitignore +++ b/usrp2/top/B100/.gitignore diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/B100/Makefile index ca6ec9320..ca6ec9320 100644 --- a/usrp2/top/u1plus/Makefile +++ b/usrp2/top/B100/Makefile diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/B100/core_compile index b2ccc8b49..b2ccc8b49 100755 --- a/usrp2/top/u1plus/core_compile +++ b/usrp2/top/B100/core_compile diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/B100/timing.ucf index b2a455f6d..b2a455f6d 100644 --- a/usrp2/top/u1plus/timing.ucf +++ b/usrp2/top/B100/timing.ucf diff --git a/usrp2/top/u1plus/u1plus.ucf b/usrp2/top/B100/u1plus.ucf index cd89878e3..cd89878e3 100644 --- a/usrp2/top/u1plus/u1plus.ucf +++ b/usrp2/top/B100/u1plus.ucf diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/B100/u1plus.v index 9aafef3ce..9aafef3ce 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/B100/u1plus.v diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 898f5950c..898f5950c 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/E1x0/.gitignore index 8d872713e..8d872713e 100644 --- a/usrp2/top/u1e/.gitignore +++ b/usrp2/top/E1x0/.gitignore diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/E1x0/Makefile index 5d721979b..5d721979b 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/E1x0/Makefile diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/E1x0/Makefile.passthru index f2d835608..f2d835608 100644 --- a/usrp2/top/u1e_passthru/Makefile +++ b/usrp2/top/E1x0/Makefile.passthru diff --git a/usrp2/top/u1e/README b/usrp2/top/E1x0/README index 14c7a4955..14c7a4955 100644 --- a/usrp2/top/u1e/README +++ b/usrp2/top/E1x0/README diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/E1x0/cmdfile index 291c723b8..291c723b8 100644 --- a/usrp2/top/u1e/cmdfile +++ b/usrp2/top/E1x0/cmdfile diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/E1x0/core_compile index dc0cd081e..dc0cd081e 100755 --- a/usrp2/top/u1e/core_compile +++ b/usrp2/top/E1x0/core_compile diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/E1x0/make.sim index 1c163884c..1c163884c 100644 --- a/usrp2/top/u1e/make.sim +++ b/usrp2/top/E1x0/make.sim diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/E1x0/passthru.ucf index 64e6f0440..64e6f0440 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/E1x0/passthru.ucf diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/E1x0/passthru.v index 12e4db017..12e4db017 100644 --- a/usrp2/top/u1e_passthru/passthru.v +++ b/usrp2/top/E1x0/passthru.v diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/E1x0/tb_u1e.v index 5fc8134fb..5fc8134fb 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/E1x0/tb_u1e.v diff --git a/usrp2/top/u1e/timing.ucf b/usrp2/top/E1x0/timing.ucf index 8df28c9d3..8df28c9d3 100644 --- a/usrp2/top/u1e/timing.ucf +++ b/usrp2/top/E1x0/timing.ucf diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/E1x0/u1e.ucf index 0c487a601..0c487a601 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/E1x0/u1e.ucf diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/E1x0/u1e.v index 445b14a03..445b14a03 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/E1x0/u1e.v diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index d10a3ab30..d10a3ab30 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v diff --git a/usrp2/top/u1e_passthru/.gitignore b/usrp2/top/N2x0/.gitignore index 1b2211df0..1b2211df0 100644 --- a/usrp2/top/u1e_passthru/.gitignore +++ b/usrp2/top/N2x0/.gitignore diff --git a/usrp2/top/u2plus/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3 index a525836ed..a525836ed 100644 --- a/usrp2/top/u2plus/Makefile.N200R3 +++ b/usrp2/top/N2x0/Makefile.N200R3 diff --git a/usrp2/top/u2plus/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4 index 955aadc59..955aadc59 100644 --- a/usrp2/top/u2plus/Makefile.N200R4 +++ b/usrp2/top/N2x0/Makefile.N200R4 diff --git a/usrp2/top/u2plus/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index e29251e1c..e29251e1c 100644 --- a/usrp2/top/u2plus/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 diff --git a/usrp2/top/u2plus/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 73747e544..73747e544 100644 --- a/usrp2/top/u2plus/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/N2x0/bootloader.rmi index e5be670fb..e5be670fb 100644 --- a/usrp2/top/u2plus/bootloader.rmi +++ b/usrp2/top/N2x0/bootloader.rmi diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/N2x0/capture_ddrlvds.v index d263e0cfa..d263e0cfa 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/N2x0/capture_ddrlvds.v diff --git a/usrp2/top/u2plus/rev4_defs.v b/usrp2/top/N2x0/rev4_defs.v index e37f34851..e37f34851 100644 --- a/usrp2/top/u2plus/rev4_defs.v +++ b/usrp2/top/N2x0/rev4_defs.v diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/N2x0/u2plus.ucf index 5fbe55c26..5fbe55c26 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/N2x0/u2plus.ucf diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/N2x0/u2plus.v index 7bf467fde..7bf467fde 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/N2x0/u2plus.v diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index ee5d7efcd..ee5d7efcd 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v diff --git a/usrp2/top/u2_rev3/.gitignore b/usrp2/top/USRP2/.gitignore index f50a2b7e5..f50a2b7e5 100644 --- a/usrp2/top/u2_rev3/.gitignore +++ b/usrp2/top/USRP2/.gitignore diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/USRP2/Makefile index e9b43491a..e9b43491a 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/USRP2/Makefile diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/USRP2/u2_core.v index 0e6120ec6..0e6120ec6 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/USRP2/u2_rev3.ucf index 8017f61ff..8017f61ff 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/USRP2/u2_rev3.ucf diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/USRP2/u2_rev3.v index bc7ae5f16..bc7ae5f16 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/USRP2/u2_rev3.v diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile deleted file mode 100644 index 33a2a51c7..000000000 --- a/usrp2/top/safe_u1plus/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u1plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan3A" \ -device XC3S1400A \ -package ft256 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -top/safe_u1plus/safe_u1plus.ucf \ -top/safe_u1plus/safe_u1plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf deleted file mode 100644 index a0c743525..000000000 --- a/usrp2/top/safe_u1plus/safe_u1plus.ucf +++ /dev/null @@ -1,171 +0,0 @@ -NET "debug_led<2>" LOC = "R2" ; -NET "debug_led<1>" LOC = "N4" ; -NET "debug_led<0>" LOC = "P4" ; -NET "reset_n" LOC = "D5" ; -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; - -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "T15" ; -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; -NET "fpga_cfg_init_b" LOC = "T12" ; - - -#NET "TMS" LOC = "B2" ; -#NET "TDO" LOC = "B16" ; -#NET "TDI" LOC = "B1" ; -#NET "TCK" LOC = "A15" ; -#NET "GPIF_D07" LOC = "N12" ; -#NET "GPIF_D06" LOC = "P13" ; -#NET "GPIF_D05" LOC = "P11" ; -#NET "GPIF_RDY3" LOC = "N11" ; -#NET "GPIF_RDY2" LOC = "T10" ; -#NET "GPIF_RDY1" LOC = "T4" ; -#NET "GPIF_RDY0" LOC = "R5" ; -#NET "cgen_st_status" LOC = "P6" ; -#NET "GPIF_CTL3" LOC = "N5" ; -#NET "GPIF_CTL2" LOC = "M11" ; -#NET "GPIF_CTL1" LOC = "M9" ; -#NET "GPIF_CTL0" LOC = "M7" ; -#NET "SDA_FPGA" LOC = "T13" ; -#NET "SCL_FPGA" LOC = "R13" ; -#NET "FX2_PA7_FLAGD" LOC = "P12" ; -#NET "mystery_bus_2" LOC = "T11" ; -#NET "FX2_PA6_PKTEND" LOC = "R11" ; -#NET "FX2_PA2_SLOE" LOC = "P10" ; -#NET "GPIF_D15" LOC = "P7" ; -#NET "GPIF_D14" LOC = "N8" ; -#NET "GPIF_D13" LOC = "T5" ; -#NET "GPIF_D12" LOC = "T6" ; -#NET "GPIF_D11" LOC = "N6" ; -#NET "GPIF_D10" LOC = "P5" ; -#NET "GPIF_D09" LOC = "R3" ; -#NET "GPIF_D08" LOC = "T3" ; -#NET "cgen_ref_sel" LOC = "T2" ; -#NET "GPIF_D04" LOC = "R9" ; -#NET "GPIF_D03" LOC = "T9" ; -#NET "GPIF_D02" LOC = "N9" ; -#NET "GPIF_D01" LOC = "P9" ; -#NET "GPIF_D00" LOC = "P8" ; -#NET "IFCLK" LOC = "T8" ; -#NET "cgen_sync_b" LOC = "H15" ; -#NET "FPGA_TXD" LOC = "H16" ; -#NET "debug_00" LOC = "K16" ; -#NET "debug_01" LOC = "J16" ; -#NET "debug_clk0" LOC = "K15" ; -#NET "debug_clk1" LOC = "K14" ; -#NET "debug_02" LOC = "C16" ; -#NET "debug_03" LOC = "C15" ; -#NET "debug_04" LOC = "E13" ; -#NET "debug_05" LOC = "D14" ; -#NET "debug_06" LOC = "D16" ; -#NET "debug_07" LOC = "D15" ; -#NET "debug_08" LOC = "E14" ; -#NET "debug_09" LOC = "F13" ; -#NET "debug_10" LOC = "G13" ; -#NET "debug_11" LOC = "F14" ; -#NET "debug_12" LOC = "E16" ; -#NET "debug_13" LOC = "F15" ; -#NET "debug_14" LOC = "H13" ; -#NET "debug_15" LOC = "G14" ; -#NET "debug_16" LOC = "G16" ; -#NET "debug_17" LOC = "F16" ; -#NET "debug_18" LOC = "J12" ; -#NET "debug_19" LOC = "J13" ; -#NET "debug_20" LOC = "L14" ; -#NET "debug_21" LOC = "L16" ; -#NET "debug_22" LOC = "M15" ; -#NET "debug_23" LOC = "M16" ; -#NET "debug_24" LOC = "L13" ; -#NET "debug_25" LOC = "K13" ; -#NET "debug_26" LOC = "P16" ; -#NET "debug_27" LOC = "N16" ; -#NET "debug_28" LOC = "R15" ; -#NET "debug_29" LOC = "P15" ; -#NET "debug_30" LOC = "N13" ; -#NET "debug_31" LOC = "N14" ; -#NET "PPS_IN" LOC = "M14" ; -#NET "cgen_st_ld" LOC = "M13" ; -#NET "cgen_st_refmon" LOC = "J14" ; -#NET "FPGA_RXD" LOC = "H12" ; -#NET "DA10" LOC = "A8" ; -#NET "DA09" LOC = "B8" ; -#NET "DA08" LOC = "C8" ; -#NET "DA07" LOC = "D8" ; -#NET "DA06" LOC = "C9" ; -#NET "DA05" LOC = "A9" ; -#NET "DA04" LOC = "C10" ; -#NET "DA03" LOC = "D9" ; -#NET "SCLK_CODEC" LOC = "K3" ; -#NET "TXBLANK" LOC = "K1" ; -#NET "TXSYNC" LOC = "J2" ; -#NET "TX00" LOC = "J1" ; -#NET "TX01" LOC = "H3" ; -#NET "TX02" LOC = "J3" ; -#NET "TX03" LOC = "G2" ; -#NET "TX04" LOC = "H1" ; -#NET "TX05" LOC = "N3" ; -#NET "TX06" LOC = "M4" ; -#NET "TX07" LOC = "R1" ; -#NET "TX08" LOC = "P2" ; -#NET "TX09" LOC = "P1" ; -#NET "TX10" LOC = "M1" ; -#NET "TX11" LOC = "N1" ; -#NET "TX12" LOC = "M3" ; -#NET "TX13" LOC = "L4" ; -#NET "io_tx_00" LOC = "K4" ; -#NET "io_tx_01" LOC = "L3" ; -#NET "io_tx_02" LOC = "L2" ; -#NET "io_tx_03" LOC = "F1" ; -#NET "io_tx_04" LOC = "F3" ; -#NET "io_tx_05" LOC = "G3" ; -#NET "io_tx_06" LOC = "E3" ; -#NET "io_tx_07" LOC = "E2" ; -#NET "io_tx_08" LOC = "E4" ; -#NET "io_tx_09" LOC = "F4" ; -#NET "io_tx_10" LOC = "D1" ; -#NET "io_tx_11" LOC = "E1" ; -#NET "io_tx_12" LOC = "D4" ; -#NET "io_tx_13" LOC = "D3" ; -#NET "io_tx_14" LOC = "C2" ; -#NET "io_tx_15" LOC = "C1" ; -#NET "MISO_AUX" LOC = "J5" ; -#NET "MISO_CODEC" LOC = "G4" ; -#NET "MISO_TX_DB" LOC = "J4" ; -#NET "SEN_TX_DB" LOC = "N2" ; -#NET "MOSI_TX_DB" LOC = "L1" ; -#NET "SCLK_TX_DB" LOC = "G1" ; -#NET "DA02" LOC = "A3" ; -#NET "DA01" LOC = "B3" ; -#NET "DA00" LOC = "A4" ; -#NET "SEN_RX_DB" LOC = "B4" ; -#NET "MOSI_RX_DB" LOC = "A5" ; -#NET "SCLK_RX_DB" LOC = "C5" ; -#NET "io_rx_00" LOC = "D7" ; -#NET "io_rx_01" LOC = "C6" ; -#NET "io_rx_02" LOC = "A6" ; -#NET "io_rx_03" LOC = "B6" ; -#NET "io_rx_04" LOC = "E9" ; -#NET "io_rx_05" LOC = "A7" ; -#NET "io_rx_06" LOC = "C7" ; -#NET "io_rx_07" LOC = "B10" ; -#NET "io_rx_08" LOC = "A10" ; -#NET "io_rx_09" LOC = "C11" ; -#NET "io_rx_10" LOC = "A11" ; -#NET "io_rx_11" LOC = "D11" ; -#NET "io_rx_12" LOC = "B12" ; -#NET "io_rx_13" LOC = "A12" ; -#NET "io_rx_14" LOC = "A14" ; -#NET "io_rx_15" LOC = "A13" ; -#NET "SEN_AUX" LOC = "C12" ; -#NET "SCLK_AUX" LOC = "D12" ; -#NET "reset_codec" LOC = "B14" ; -#NET "SEN_CODEC" LOC = "D13" ; -#NET "MOSI_CODEC" LOC = "C13" ; -#NET "MISO_RX_DB" LOC = "E6" ; -#NET "mystery_bus_1" LOC = "C4" ; -#NET "mystery_bus_0" LOC = "E7" ; -#NET "RXSYNC" LOC = "D10" ; -#NET "DA11" LOC = "B15" ; - diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v deleted file mode 100644 index e55c7f0be..000000000 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u1plus - (input CLK_FPGA_P, input CLK_FPGA_N, - input reset_n, - output [2:0] debug_led, // LED4 is shared w/INIT_B - output fpga_cfg_init_b - ); - - assign fpga_cfg_init_b = 1; - - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign debug_led[1:0] = ~ctr[26:25]; - - assign debug_led[2] = ~reset_n; - -endmodule // safe_u1plus diff --git a/usrp2/top/safe_u2plus/.gitignore b/usrp2/top/safe_u2plus/.gitignore deleted file mode 100644 index a96f0be92..000000000 --- a/usrp2/top/safe_u2plus/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -build* -*impact* diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile deleted file mode 100644 index b72241050..000000000 --- a/usrp2/top/safe_u2plus/Makefile +++ /dev/null @@ -1,245 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u2plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2plus/capture_ddrlvds.v \ -top/safe_u2plus/u2plus.ucf \ -top/safe_u2plus/safe_u2plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u2plus/safe_u2plus.v b/usrp2/top/safe_u2plus/safe_u2plus.v deleted file mode 100644 index dca9688c5..000000000 --- a/usrp2/top/safe_u2plus/safe_u2plus.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [5:1] leds, // LED4 is shared w/INIT_B - output ETH_LED - ); - - wire clk_fpga; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign {leds,ETH_LED} = ~ctr[29:24]; - -endmodule // safe_u2plus diff --git a/usrp2/top/safe_u2plus/u2plus.ucf b/usrp2/top/safe_u2plus/u2plus.ucf deleted file mode 100755 index 0a9460d86..000000000 --- a/usrp2/top/safe_u2plus/u2plus.ucf +++ /dev/null @@ -1,401 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -#NET "ADC_clkout_p" LOC = "P1" ; -#NET "ADC_clkout_n" LOC = "P2" ; -#NET "ADCA_12_p" LOC = "Y1" ; -#NET "ADCA_12_n" LOC = "Y2" ; -#NET "ADCA_10_p" LOC = "W3" ; -#NET "ADCA_10_n" LOC = "W4" ; -#NET "ADCA_8_p" LOC = "T7" ; -#NET "ADCA_8_n" LOC = "U6" ; -#NET "ADCA_6_p" LOC = "U5" ; -#NET "ADCA_6_n" LOC = "V5" ; -#NET "ADCA_4_p" LOC = "T10" ; -#NET "ADCA_4_n" LOC = "T9" ; -#NET "ADCA_2_p" LOC = "V1" ; -#NET "ADCA_2_n" LOC = "V2" ; -#NET "ADCA_0_p" LOC = "R8" ; -#NET "ADCA_0_n" LOC = "R7" ; -#NET "ADCB_2_p" LOC = "U7" ; -#NET "ADCB_2_n" LOC = "U8" ; -#NET "ADCB_0_p" LOC = "AA2" ; -#NET "ADCB_0_n" LOC = "AA3" ; -#NET "ADCB_4_p" LOC = "AE1" ; -#NET "ADCB_4_n" LOC = "AE2" ; -#NET "ADCB_6_p" LOC = "W1" ; -#NET "ADCB_6_n" LOC = "W2" ; -#NET "ADCB_8_p" LOC = "U3" ; -#NET "ADCB_8_n" LOC = "V4" ; -#NET "ADCB_10_p" LOC = "J1" ; -#NET "ADCB_10_n" LOC = "K1" ; -#NET "ADCB_12_p" LOC = "J3" ; -#NET "ADCB_12_n" LOC = "J2" ; - -## DAC -#NET "DAC_LOCK" LOC = "P4" ; -#NET "DACA<0>" LOC = "P8" ; -#NET "DACA<1>" LOC = "P9" ; -#NET "DACA<2>" LOC = "R5" ; -#NET "DACA<3>" LOC = "R6" ; -#NET "DACA<4>" LOC = "P7" ; -#NET "DACA<5>" LOC = "P6" ; -#NET "DACA<6>" LOC = "T3" ; -#NET "DACA<7>" LOC = "T4" ; -#NET "DACA<8>" LOC = "R3" ; -#NET "DACA<9>" LOC = "R4" ; -#NET "DACA<10>" LOC = "R2" ; -#NET "DACA<11>" LOC = "N1" ; -#NET "DACA<12>" LOC = "N2" ; -#NET "DACA<13>" LOC = "N5" ; -#NET "DACA<14>" LOC = "N4" ; -#NET "DACA<15>" LOC = "M2" ; -#NET "DACB<0>" LOC = "M5" ; -#NET "DACB<1>" LOC = "M6" ; -#NET "DACB<2>" LOC = "M4" ; -#NET "DACB<3>" LOC = "M3" ; -#NET "DACB<4>" LOC = "M8" ; -#NET "DACB<5>" LOC = "M7" ; -#NET "DACB<6>" LOC = "L4" ; -#NET "DACB<7>" LOC = "L3" ; -#NET "DACB<8>" LOC = "K3" ; -#NET "DACB<9>" LOC = "K2" ; -#NET "DACB<10>" LOC = "K5" ; -#NET "DACB<11>" LOC = "K4" ; -#NET "DACB<12>" LOC = "M10" ; -#NET "DACB<13>" LOC = "M9" ; -#NET "DACB<14>" LOC = "J5" ; -#NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -#NET "io_tx<15>" LOC = "K6" ; -#NET "io_tx<14>" LOC = "L7" ; -#NET "io_tx<13>" LOC = "H2" ; -#NET "io_tx<12>" LOC = "H1" ; -#NET "io_tx<11>" LOC = "L10" ; -#NET "io_tx<10>" LOC = "L9" ; -#NET "io_tx<9>" LOC = "G3" ; -#NET "io_tx<8>" LOC = "F3" ; -#NET "io_tx<7>" LOC = "K7" ; -#NET "io_tx<6>" LOC = "J6" ; -#NET "io_tx<5>" LOC = "E1" ; -#NET "io_tx<4>" LOC = "F2" ; -#NET "io_tx<3>" LOC = "J7" ; -#NET "io_tx<2>" LOC = "H6" ; -#NET "io_tx<1>" LOC = "F5" ; -#NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -#NET "io_rx<15>" LOC = "AD1" ; -#NET "io_rx<14>" LOC = "AD2" ; -#NET "io_rx<13>" LOC = "AC2" ; -#NET "io_rx<12>" LOC = "AC3" ; -#NET "io_rx<11>" LOC = "W7" ; -#NET "io_rx<10>" LOC = "W6" ; -#NET "io_rx<9>" LOC = "U9" ; -#NET "io_rx<8>" LOC = "V8" ; -#NET "io_rx<7>" LOC = "AB1" ; -#NET "io_rx<6>" LOC = "AC1" ; -#NET "io_rx<5>" LOC = "V7" ; -#NET "io_rx<4>" LOC = "V6" ; -#NET "io_rx<3>" LOC = "Y5" ; -#NET "io_rx<2>" LOC = "R10" ; -#NET "io_rx<1>" LOC = "R1" ; -#NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -#NET "FPGA_RESET" LOC = "K24" ; - -## Debug -#NET "debug_clk<0>" LOC = "AA10" ; -#NET "debug_clk<1>" LOC = "AD11" ; -#NET "debug<0>" LOC = "AC19" ; -#NET "debug<1>" LOC = "AF20" ; -#NET "debug<2>" LOC = "AE20" ; -#NET "debug<3>" LOC = "AC16" ; -#NET "debug<4>" LOC = "AB16" ; -#NET "debug<5>" LOC = "AF19" ; -#NET "debug<6>" LOC = "AE19" ; -#NET "debug<7>" LOC = "V15" ; -#NET "debug<8>" LOC = "U15" ; -#NET "debug<9>" LOC = "AE17" ; -#NET "debug<10>" LOC = "AD17" ; -#NET "debug<11>" LOC = "V14" ; -#NET "debug<12>" LOC = "W15" ; -#NET "debug<13>" LOC = "AC15" ; -#NET "debug<14>" LOC = "AD14" ; -#NET "debug<15>" LOC = "AC14" ; -#NET "debug<16>" LOC = "AC11" ; -#NET "debug<17>" LOC = "AB12" ; -#NET "debug<18>" LOC = "AC12" ; -#NET "debug<19>" LOC = "V13" ; -#NET "debug<20>" LOC = "W13" ; -#NET "debug<21>" LOC = "AE8" ; -#NET "debug<22>" LOC = "AF8" ; -#NET "debug<23>" LOC = "V12" ; -#NET "debug<24>" LOC = "W12" ; -#NET "debug<25>" LOC = "AB9" ; -#NET "debug<26>" LOC = "AC9" ; -#NET "debug<27>" LOC = "AC8" ; -#NET "debug<28>" LOC = "AB7" ; -#NET "debug<29>" LOC = "V11" ; -#NET "debug<30>" LOC = "U11" ; -#NET "debug<31>" LOC = "Y10" ; - -## UARTS -#NET "TXD<3>" LOC = "AD20" ; -#NET "TXD<2>" LOC = "AC20" ; -#NET "TXD<1>" LOC = "AD19" ; -#NET "RXD<3>" LOC = "AF17" ; -#NET "RXD<2>" LOC = "AF15" ; -#NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -#NET "CLK_STATUS" LOC = "AD22" ; -#NET "CLK_FUNC" LOC = "AC21" ; -#NET "clk_sel<0>" LOC = "AE21" ; -#NET "clk_sel<1>" LOC = "AD21" ; -#NET "clk_en<1>" LOC = "AA17" ; -#NET "clk_en<0>" LOC = "Y17" ; - -## I2C -#NET "SDA" LOC = "V16" ; -#NET "SCL" LOC = "U16" ; - -## Timing -#NET "PPS_IN" LOC = "AB6" ; -#NET "PPS2_IN" LOC = "AA20" ; - -## SPI -#NET "SEN_CLK" LOC = "AA18" ; -#NET "MOSI_CLK" LOC = "W17" ; -#NET "SCLK_CLK" LOC = "V17" ; -#NET "MISO_CLK" LOC = "AC10" ; - -#NET "SEN_DAC" LOC = "AE7" ; -#NET "SCLK_DAC" LOC = "AF5" ; -#NET "MOSI_DAC" LOC = "AE6" ; -#NET "MISO_DAC" LOC = "Y3" ; - -#NET "SCLK_ADC" LOC = "B1" ; -#NET "MOSI_ADC" LOC = "J8" ; -#NET "SEN_ADC" LOC = "J9" ; - -#NET "MOSI_TX_ADC" LOC = "V10" ; -#NET "SEN_TX_ADC" LOC = "W10" ; -#NET "SCLK_TX_ADC" LOC = "AC6" ; -#NET "MISO_TX_ADC" LOC = "G1" ; - -#NET "MOSI_TX_DAC" LOC = "AD6" ; -#NET "SEN_TX_DAC" LOC = "AE4" ; -#NET "SCLK_TX_DAC" LOC = "AF4" ; - -#NET "SCLK_TX_DB" LOC = "AE3" ; -#NET "MOSI_TX_DB" LOC = "AF3" ; -#NET "SEN_TX_DB" LOC = "W9" ; -#NET "MISO_TX_DB" LOC = "AA5" ; - -#NET "MOSI_RX_ADC" LOC = "E3" ; -#NET "SCLK_RX_ADC" LOC = "F4" ; -#NET "SEN_RX_ADC" LOC = "D3" ; -#NET "MISO_RX_ADC" LOC = "C1" ; - -#NET "SCLK_RX_DAC" LOC = "E4" ; -#NET "SEN_RX_DAC" LOC = "K9" ; -#NET "MOSI_RX_DAC" LOC = "K8" ; - -#NET "SCLK_RX_DB" LOC = "G6" ; -#NET "MOSI_RX_DB" LOC = "H7" ; -#NET "SEN_RX_DB" LOC = "B2" ; -#NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -#NET "CLK_TO_MAC" LOC = "P26" ; - -#NET "GMII_TXD<7>" LOC = "G21" ; -#NET "GMII_TXD<6>" LOC = "C26" ; -#NET "GMII_TXD<5>" LOC = "C25" ; -#NET "GMII_TXD<4>" LOC = "J21" ; -#NET "GMII_TXD<3>" LOC = "H21" ; -#NET "GMII_TXD<2>" LOC = "D25" ; -#NET "GMII_TXD<1>" LOC = "D24" ; -#NET "GMII_TXD<0>" LOC = "E26" ; -#NET "GMII_TX_EN" LOC = "D26" ; -#NET "GMII_TX_ER" LOC = "J19" ; -#NET "GMII_GTX_CLK" LOC = "J20" ; -#NET "GMII_TX_CLK" LOC = "P25" ; - -#NET "GMII_RX_CLK" LOC = "P21" ; -#NET "GMII_RXD<7>" LOC = "G22" ; -#NET "GMII_RXD<6>" LOC = "K19" ; -#NET "GMII_RXD<5>" LOC = "K18" ; -#NET "GMII_RXD<4>" LOC = "E24" ; -#NET "GMII_RXD<3>" LOC = "F23" ; -#NET "GMII_RXD<2>" LOC = "L18" ; -#NET "GMII_RXD<1>" LOC = "L17" ; -#NET "GMII_RXD<0>" LOC = "F25" ; -#NET "GMII_RX_DV" LOC = "F24" ; -#NET "GMII_RX_ER" LOC = "L20" ; -#NET "GMII_CRS" LOC = "K20" ; -#NET "GMII_COL" LOC = "G23" ; - -#NET "PHY_INTn" LOC = "L22" ; -#NET "MDIO" LOC = "K21" ; -#NET "MDC" LOC = "J23" ; -#NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" ; - -## MIMO Interface -#NET "exp_time_out_p" LOC = "Y14" ; -#NET "exp_time_out_n" LOC = "AA14" ; -#NET "exp_time_in_p" LOC = "N18" ; -#NET "exp_time_in_n" LOC = "N17" ; -#NET "exp_user_out_p" LOC = "AF14" ; -#NET "exp_user_out_n" LOC = "AE14" ; -#NET "exp_user_in_p" LOC = "L24" ; -#NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -#NET "ser_enable" LOC = "R20" ; -#NET "ser_prbsen" LOC = "U23" ; -#NET "ser_loopen" LOC = "R19" ; -#NET "ser_rx_en" LOC = "Y21" ; -#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -#NET "ser_t<15>" LOC = "V23" ; -#NET "ser_t<14>" LOC = "U22" ; -#NET "ser_t<13>" LOC = "V24" ; -#NET "ser_t<12>" LOC = "V25" ; -#NET "ser_t<11>" LOC = "W23" ; -#NET "ser_t<10>" LOC = "V22" ; -#NET "ser_t<9>" LOC = "T18" ; -#NET "ser_t<8>" LOC = "T17" ; -#NET "ser_t<7>" LOC = "Y24" ; -#NET "ser_t<6>" LOC = "Y25" ; -#NET "ser_t<5>" LOC = "U21" ; -#NET "ser_t<4>" LOC = "T20" ; -#NET "ser_t<3>" LOC = "Y22" ; -#NET "ser_t<2>" LOC = "Y23" ; -#NET "ser_t<1>" LOC = "U19" ; -#NET "ser_t<0>" LOC = "U18" ; -#NET "ser_tkmsb" LOC = "AA24" ; -#NET "ser_tklsb" LOC = "AA25" ; -#NET "ser_rx_clk" LOC = "P18" ; -#NET "ser_r<15>" LOC = "V21" ; -#NET "ser_r<14>" LOC = "U20" ; -#NET "ser_r<13>" LOC = "AA22" ; -#NET "ser_r<12>" LOC = "AA23" ; -#NET "ser_r<11>" LOC = "V18" ; -#NET "ser_r<10>" LOC = "V19" ; -#NET "ser_r<9>" LOC = "AB23" ; -#NET "ser_r<8>" LOC = "AC26" ; -#NET "ser_r<7>" LOC = "AB26" ; -#NET "ser_r<6>" LOC = "AD26" ; -#NET "ser_r<5>" LOC = "AC25" ; -#NET "ser_r<4>" LOC = "W20" ; -#NET "ser_r<3>" LOC = "W21" ; -#NET "ser_r<2>" LOC = "AC23" ; -#NET "ser_r<1>" LOC = "AC24" ; -#NET "ser_r<0>" LOC = "AE26" ; -#NET "ser_rkmsb" LOC = "AD25" ; -#NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -#NET "RAM_D<35>" LOC = "K16" ; -#NET "RAM_D<34>" LOC = "D20" ; -#NET "RAM_D<33>" LOC = "C20" ; -#NET "RAM_D<32>" LOC = "E21" ; -#NET "RAM_D<31>" LOC = "D21" ; -#NET "RAM_D<30>" LOC = "C21" ; -#NET "RAM_D<29>" LOC = "B21" ; -#NET "RAM_D<28>" LOC = "H17" ; -#NET "RAM_D<27>" LOC = "G17" ; -#NET "RAM_D<26>" LOC = "B23" ; -#NET "RAM_D<25>" LOC = "A22" ; -#NET "RAM_D<24>" LOC = "D23" ; -#NET "RAM_D<23>" LOC = "C23" ; -#NET "RAM_D<22>" LOC = "D22" ; -#NET "RAM_D<21>" LOC = "C22" ; -#NET "RAM_D<20>" LOC = "F19" ; -#NET "RAM_D<19>" LOC = "G20" ; -#NET "RAM_D<18>" LOC = "F20" ; -#NET "RAM_D<17>" LOC = "F7" ; -#NET "RAM_D<16>" LOC = "E7" ; -#NET "RAM_D<15>" LOC = "G9" ; -#NET "RAM_D<14>" LOC = "H9" ; -#NET "RAM_D<13>" LOC = "G10" ; -#NET "RAM_D<12>" LOC = "H10" ; -#NET "RAM_D<11>" LOC = "A4" ; -#NET "RAM_D<10>" LOC = "B4" ; -#NET "RAM_D<9>" LOC = "C5" ; -#NET "RAM_D<8>" LOC = "D6" ; -#NET "RAM_D<7>" LOC = "J11" ; -#NET "RAM_D<6>" LOC = "K11" ; -#NET "RAM_D<5>" LOC = "B7" ; -#NET "RAM_D<4>" LOC = "C7" ; -#NET "RAM_D<3>" LOC = "B6" ; -#NET "RAM_D<2>" LOC = "C6" ; -#NET "RAM_D<1>" LOC = "C8" ; -#NET "RAM_D<0>" LOC = "D8" ; -#NET "RAM_A<0>" LOC = "C11" ; -#NET "RAM_A<1>" LOC = "E12" ; -#NET "RAM_A<2>" LOC = "F12" ; -#NET "RAM_A<3>" LOC = "D13" ; -#NET "RAM_A<4>" LOC = "C12" ; -#NET "RAM_A<5>" LOC = "A12" ; -#NET "RAM_A<6>" LOC = "B12" ; -#NET "RAM_A<7>" LOC = "E14" ; -#NET "RAM_A<8>" LOC = "F14" ; -#NET "RAM_A<9>" LOC = "B15" ; -#NET "RAM_A<10>" LOC = "A15" ; -#NET "RAM_A<11>" LOC = "D16" ; -#NET "RAM_A<12>" LOC = "C15" ; -#NET "RAM_A<13>" LOC = "D17" ; -#NET "RAM_A<14>" LOC = "C16" ; -#NET "RAM_A<15>" LOC = "F15" ; -#NET "RAM_A<16>" LOC = "C17" ; -#NET "RAM_A<17>" LOC = "B17" ; -#NET "RAM_A<18>" LOC = "B18" ; -#NET "RAM_A<19>" LOC = "A18" ; -#NET "RAM_A<20>" LOC = "D18" ; -#NET "RAM_BWn<3>" LOC = "D9" ; -#NET "RAM_BWn<2>" LOC = "A9" ; -#NET "RAM_BWn<1>" LOC = "B9" ; -#NET "RAM_BWn<0>" LOC = "G12" ; -#NET "RAM_ZZ" LOC = "J12" ; -#NET "RAM_LDn" LOC = "H12" ; -#NET "RAM_OEn" LOC = "C10" ; -#NET "RAM_WEn" LOC = "D10" ; -#NET "RAM_CENn" LOC = "B10" ; -#NET "RAM_CLK" LOC = "A10" ; - -## SPI Flash -#NET "flash_miso" LOC = "AF24" ; -#NET "flash_clk" LOC = "AE24" ; -#NET "flash_mosi" LOC = "AB15" ; -#NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -##NET "PROG_B" LOC = "A2" ; -##NET "PUDC_B" LOC = "G8" ; -##NET "DONE" LOC = "AB21" ; -##NET "INIT_B" LOC = "AA15" ; - - -##NET "unnamed_net19" LOC = "AE9" ; # VS1 -##NET "unnamed_net18" LOC = "AF9" ; # VS0 -##NET "unnamed_net17" LOC = "AA12" ; # VS2 -##NET "unnamed_net16" LOC = "Y7" ; # M2 -##NET "unnamed_net15" LOC = "AC4" ; # M1 -##NET "unnamed_net14" LOC = "AD4" ; # M0 -##NET "unnamed_net13" LOC = "D4" ; # TMS -##NET "unnamed_net12" LOC = "E23" ; # TDO -##NET "unnamed_net11" LOC = "G7" ; # TDI -##NET "unnamed_net10" LOC = "A25" ; # TCK -##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/usrp2/top/single_u2_sim/single_u2_sim.v b/usrp2/top/single_u2_sim/single_u2_sim.v deleted file mode 100644 index 2a7b24849..000000000 --- a/usrp2/top/single_u2_sim/single_u2_sim.v +++ /dev/null @@ -1,324 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module single_u2_sim(); - // Misc, debug - wire [7:0] leds; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_on_a, adc_oe_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_on_b, adc_oe_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - reg clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #6 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #5 clk_fpga = ~clk_fpga; - - initial clk_to_mac = 0; - always #4 clk_to_mac = ~clk_to_mac; - - wire div_clk, dsp_clk; - reg [7:0] div_ctr = 0; - - assign dsp_clk = clock_ready ? clk_fpga : aux_clk; - assign wb_clk = div_clk; - -`define CLK_DIV_2 1 -//`define CLK_DIV_3 - -`ifdef CLK_DIV_2 - localparam clock_divider = 4'd2; - always @(posedge dsp_clk) - div_ctr <= div_ctr + 1; - assign div_clk = div_ctr[0]; -`endif - -`ifdef CLK_DIV_3 - localparam clock_divider = 2; - always @(posedge dsp_clk or negedge dsp_clk) - if(div_ctr == 5) - div_ctr <= 0; - else - div_ctr <= div_ctr + 1; - assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); -`endif - - initial - $monitor($time, ,clock_ready); - - always #1000000 $monitor("Time in ns ",$time); - - initial begin - @(negedge cpld_done); - @(posedge cpld_done); - $dumpfile("single_u2_sim.lxt"); - $dumpvars(0,single_u2_sim); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(0),.error(0) ); - - adc_model adc_model - (.clk(dsp_clk),.rst(0), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); - - wire [2:0] speed; - phy_sim phy_model - (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), - .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), - .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), - .Crs(GMII_CRS), .Col(GMII_COL), - .Speed(speed), .Done(0) ); - pullup p3(MDIO); - - miim_model miim_model - (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), - .phy_intn_o(PHY_INTn),.speed_o(speed) ); - - xlnx_glbl glbl (.GSR(),.GTS()); - - wire RAM_MODE = 1'b0; - cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), - .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), - .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), - .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); - - M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), - .SDA(SDA),.SCL(SCL),.RESET(0)); - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o; - wire sda_pad_i, sda_pad_o, sda_pad_oen_o; - - pullup p1(SCL); - pullup p2(SDA); - - assign scl_pad_i = SCL; - assign sda_pad_i = SDA; - - assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; - assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; - - // printf output - wire uart_baud_o, uart_tx_o, uart_rx_i; - assign uart_rx_i = 1'b1; - - uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); - - // End the simulation - always @(posedge wb_clk) - if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) - begin - $display($time, "Finish called.",); - $finish; - end - - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_init_b (1), - .por (0), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (uart_baud_o), - .sim_mode (1'b1), - .clock_divider (clock_divider) - ); - -endmodule // single_u2_sim diff --git a/usrp2/top/u1plus/.gitignore b/usrp2/top/u1plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/u1plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/usrp2/top/u2plus/.gitignore b/usrp2/top/u2plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/u2plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* |