diff options
Diffstat (limited to 'usrp2/top')
| -rwxr-xr-x | usrp2/top/u1e/core_compile | 3 | ||||
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 28 |
2 files changed, 11 insertions, 20 deletions
diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/u1e/core_compile index fb1b2a854..dc0cd081e 100755 --- a/usrp2/top/u1e/core_compile +++ b/usrp2/top/u1e/core_compile @@ -1,2 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 1e3b08465..3ec4c2dd2 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -120,18 +120,15 @@ module u1e_core wire rx_eof = rx_data[33]; wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; // ///////////////////////////////////////////////////////////////////////// // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx1_dst_rdy, rx1_src_rdy; - wire [100:0] rx1_data; - wire run_rx; + wire [31:0] sample_rx; + wire strobe_rx, run_rx; wire [35:0] vita_rx_data; wire vita_rx_src_rdy, vita_rx_dst_rdy; - + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -139,20 +136,13 @@ module u1e_core .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), - .debug_rx(vrc_debug)); - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), - .debug_rx(vrf_debug) ); + .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), + .debug(vr_debug) ); fifo36_mux #(.prio(0)) mux_err_stream (.clk(wb_clk), .reset(wb_rst), .clear(0), @@ -416,7 +406,7 @@ module u1e_core */ assign debug = debug_gpmc; - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vt; |