2 files changed, 6 insertions, 6 deletions
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v
index 7e1bd2ea7..9aafef3ce 100644
--- a/usrp2/top/u1plus/u1plus.v
+++ b/usrp2/top/u1plus/u1plus.v
@@ -126,13 +126,13 @@ module u1plus
    always @(posedge clk_fpga)
      if(rxsync_0)
        begin
-	  rx_i <= rx_a;
-	  rx_q <= rx_b;
+	  rx_i <= rx_b;
+	  rx_q <= rx_a;
        end
      else
        begin
-	  rx_i <= rx_b;
-	  rx_q <= rx_a;
+	  rx_i <= rx_a;
+	  rx_q <= rx_b;
        end
    
    // /////////////////////////////////////////////////////////////////////////
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index 26565afa6..898f5950c 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -329,7 +329,7 @@ module u1plus_core
 		.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
 		.dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
 		.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
-		.gpio( /*{io_tx,io_rx}*/ ) );
+		.gpio( {io_tx,io_rx} ) );
 
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #8 + 9
@@ -387,6 +387,6 @@ module u1plus_core
    assign debug = debug0;
    assign debug_gpio_0 = 0;
    assign debug_gpio_1 = 0;
-   assign {io_tx,io_rx} = vr_debug;
+   //assign {io_tx,io_rx} = {debug1};
    
 endmodule // u1plus_core