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-rw-r--r--usrp2/top/u1e/.gitignore4
-rw-r--r--usrp2/top/u1e/Makefile246
-rw-r--r--usrp2/top/u1e/u1e.ucf262
-rw-r--r--usrp2/top/u1e/u1e.v41
4 files changed, 553 insertions, 0 deletions
diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore
new file mode 100644
index 000000000..f8b57ea21
--- /dev/null
+++ b/usrp2/top/u1e/.gitignore
@@ -0,0 +1,4 @@
+*~
+build
+*.log
+*.cmd
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
new file mode 100644
index 000000000..e9c101226
--- /dev/null
+++ b/usrp2/top/u1e/Makefile
@@ -0,0 +1,246 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u1e
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u1e/u1e.ucf \
+top/u1e/u1e.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
new file mode 100644
index 000000000..cb6d6372e
--- /dev/null
+++ b/usrp2/top/u1e/u1e.ucf
@@ -0,0 +1,262 @@
+
+NET "CLK_FPGA_P" LOC = "Y11" ;
+NET "CLK_FPGA_N" LOC = "Y10" ;
+
+## GPMC
+NET "EM_CLK" LOC = "F11" ;
+
+NET "EM_D<15>" LOC = "D13" ;
+NET "EM_D<14>" LOC = "D15" ;
+NET "EM_D<13>" LOC = "C16" ;
+NET "EM_D<12>" LOC = "B20" ;
+NET "EM_D<11>" LOC = "A19" ;
+NET "EM_D<10>" LOC = "A17" ;
+NET "EM_D<9>" LOC = "E15" ;
+NET "EM_D<8>" LOC = "F15" ;
+NET "EM_D<7>" LOC = "E16" ;
+NET "EM_D<6>" LOC = "F16" ;
+NET "EM_D<5>" LOC = "B17" ;
+NET "EM_D<4>" LOC = "C17" ;
+NET "EM_D<3>" LOC = "B19" ;
+NET "EM_D<2>" LOC = "D19" ;
+NET "EM_D<1>" LOC = "C19" ;
+NET "EM_D<0>" LOC = "A20" ;
+
+NET "EM_A<10>" LOC = "C14" ;
+NET "EM_A<9>" LOC = "C10" ;
+NET "EM_A<8>" LOC = "C5" ;
+NET "EM_A<7>" LOC = "A18" ;
+NET "EM_A<6>" LOC = "A15" ;
+NET "EM_A<5>" LOC = "A12" ;
+NET "EM_A<4>" LOC = "A10" ;
+NET "EM_A<3>" LOC = "E7" ;
+NET "EM_A<2>" LOC = "A7" ;
+NET "EM_A<1>" LOC = "C15" ;
+
+#NET "EM_NCS6" LOC = "E17" ;
+#NET "EM_NCS5" LOC = "E10" ;
+NET "EM_NCS4" LOC = "E6" ;
+#NET "EM_NCS1" LOC = "D18" ;
+#NET "EM_NCS0" LOC = "D17" ;
+
+NET "EM_WAIT0" LOC = "F14" ;
+#NET "EM_NBE1" LOC = "D14" ;
+#NET "EM_NBE0" LOC = "A13" ;
+NET "EM_NWP" LOC = "F13" ;
+NET "EM_NWE" LOC = "B13" ;
+NET "EM_NOE" LOC = "A14" ;
+NET "EM_NADV_ALE" LOC = "B15" ;
+
+
+## Overo GPIO
+#NET "overo_gpio0" LOC = "F9" ;
+#NET "overo_gpio14" LOC = "C4" ;
+#NET "overo_gpio21" LOC = "D5" ;
+#NET "overo_gpio22" LOC = "A3" ;
+#NET "overo_gpio23" LOC = "B3" ;
+#NET "overo_gpio64" LOC = "A4" ;
+#NET "overo_gpio65" LOC = "F8" ;
+#NET "overo_gpio127" LOC = "C8" ;
+#NET "overo_gpio128" LOC = "G8" ;
+#NET "overo_gpio144" LOC = "A5" ;
+#NET "overo_gpio145" LOC = "C7" ;
+#NET "overo_gpio146" LOC = "A6" ;
+#NET "overo_gpio147" LOC = "B6" ;
+#NET "overo_gpio163" LOC = "D7" ;
+#NET "overo_gpio170" LOC = "E8" ;
+#NET "overo_gpio176" LOC = "B4" ;
+
+## Overo UART
+#NET "overo_txd1" LOC = "C6" ;
+#NET "overo_rxd1" LOC = "D6" ;
+
+#NET "FPGA_TXD" LOC = "U1" ;
+#NET "FPGA_RXD" LOC = "T6" ;
+
+#NET "SYSEN" LOC = "C11" ;
+
+#NET "db_scl" LOC = "U4" ;
+#NET "db_sda" LOC = "U5" ;
+#NET "db_sclk_rx" LOC = "W3" ;
+#NET "db_miso_rx" LOC = "W2" ;
+#NET "db_mosi_rx" LOC = "V4" ;
+#NET "db_sen_rx" LOC = "V3" ;
+#NET "db_sclk_tx" LOC = "Y1" ;
+#NET "db_miso_tx" LOC = "W1" ;
+#NET "db_mosi_tx" LOC = "R3" ;
+#NET "db_sen_tx" LOC = "T4" ;
+
+## Clock Gen
+#NET "cgen_miso" LOC = "U2" ;
+#NET "cgen_mosi" LOC = "V1" ;
+#NET "cgen_sclk" LOC = "R5" ;
+#NET "cgen_sen_b" LOC = "T1" ;
+#NET "cgen_st_status" LOC = "D4" ;
+#NET "cgen_st_ld" LOC = "D1" ;
+#NET "cgen_st_refmon" LOC = "E1" ;
+#NET "cgen_sync_b" LOC = "M1" ;
+#NET "cgen_ref_sel" LOC = "J1" ;
+
+## Debug pins
+NET "debug_led<2>" LOC = "T5" ;
+NET "debug_led<1>" LOC = "R2" ;
+NET "debug_led<0>" LOC = "R1" ;
+NET "debug<0>" LOC = "P6" ;
+NET "debug<1>" LOC = "R6" ;
+NET "debug<2>" LOC = "P1" ;
+NET "debug<3>" LOC = "P2" ;
+NET "debug<4>" LOC = "N6" ;
+NET "debug<5>" LOC = "N5" ;
+NET "debug<6>" LOC = "N1" ;
+NET "debug<7>" LOC = "K2" ;
+NET "debug<8>" LOC = "K3" ;
+NET "debug<9>" LOC = "K6" ;
+NET "debug<10>" LOC = "L5" ;
+NET "debug<11>" LOC = "H2" ;
+NET "debug<12>" LOC = "K4" ;
+NET "debug<13>" LOC = "K5" ;
+NET "debug<14>" LOC = "G1" ;
+NET "debug<15>" LOC = "H1" ;
+NET "debug<16>" LOC = "H5" ;
+NET "debug<17>" LOC = "H6" ;
+NET "debug<18>" LOC = "E3" ;
+NET "debug<19>" LOC = "E4" ;
+NET "debug<20>" LOC = "G5" ;
+NET "debug<21>" LOC = "G6" ;
+NET "debug<22>" LOC = "F2" ;
+NET "debug<23>" LOC = "F1" ;
+NET "debug<24>" LOC = "H3" ;
+NET "debug<25>" LOC = "H4" ;
+NET "debug<26>" LOC = "F4" ;
+NET "debug<27>" LOC = "F5" ;
+NET "debug<28>" LOC = "C2" ;
+NET "debug<29>" LOC = "C1" ;
+NET "debug<30>" LOC = "F3" ;
+NET "debug<31>" LOC = "G3" ;
+NET "debug_clk<0>" LOC = "L6" ;
+NET "debug_clk<1>" LOC = "M5" ;
+
+#NET "debug_pb<2>" LOC = "Y2" ;
+#NET "debug_pb<1>" LOC = "AA1" ;
+#NET "debug_pb<0>" LOC = "N3" ;
+
+#NET "dip_sw<7>" LOC = "T3" ;
+#NET "dip_sw<6>" LOC = "U3" ;
+#NET "dip_sw<5>" LOC = "M3" ;
+#NET "dip_sw<4>" LOC = "N4" ;
+#NET "dip_sw<3>" LOC = "J3" ;
+#NET "dip_sw<2>" LOC = "J4" ;
+#NET "dip_sw<1>" LOC = "J6" ;
+#NET "dip_sw<0>" LOC = "J7" ;
+
+## AD9862 Interface
+#NET "aux_sdi_codec" LOC = "F19" ;
+#NET "aux_sdo_codec" LOC = "F18" ;
+#NET "aux_sclk_codec" LOC = "D21" ;
+#NET "reset_codec" LOC = "D22" ;
+#NET "sen_codec" LOC = "D20" ;
+#NET "mosi_codec" LOC = "E19" ;
+#NET "miso_codec" LOC = "F21" ;
+#NET "sclk_codec" LOC = "E20" ;
+
+#NET "RXSYNC" LOC = "F22" ;
+
+#NET "DB<11>" LOC = "E22" ;
+#NET "DB<10>" LOC = "J19" ;
+#NET "DB<9>" LOC = "H20" ;
+#NET "DB<8>" LOC = "G19" ;
+#NET "DB<7>" LOC = "F20" ;
+#NET "DB<6>" LOC = "K16" ;
+#NET "DB<5>" LOC = "J17" ;
+#NET "DB<4>" LOC = "H22" ;
+#NET "DB<3>" LOC = "G22" ;
+#NET "DB<2>" LOC = "H17" ;
+#NET "DB<1>" LOC = "H18" ;
+#NET "DB<0>" LOC = "K20" ;
+#NET "DA<11>" LOC = "J20" ;
+#NET "DA<10>" LOC = "K19" ;
+#NET "DA<9>" LOC = "K18" ;
+#NET "DA<8>" LOC = "L22" ;
+#NET "DA<7>" LOC = "K22" ;
+#NET "DA<6>" LOC = "N22" ;
+#NET "DA<5>" LOC = "M22" ;
+#NET "DA<4>" LOC = "N20" ;
+#NET "DA<3>" LOC = "N19" ;
+#NET "DA<2>" LOC = "R22" ;
+#NET "DA<1>" LOC = "P22" ;
+#NET "DA<0>" LOC = "N17" ;
+
+#NET "TX<13>" LOC = "P19" ;
+#NET "TX<12>" LOC = "R18" ;
+#NET "TX<11>" LOC = "U20" ;
+#NET "TX<10>" LOC = "T20" ;
+#NET "TX<9>" LOC = "R19" ;
+#NET "TX<8>" LOC = "R20" ;
+#NET "TX<7>" LOC = "W22" ;
+#NET "TX<6>" LOC = "Y22" ;
+#NET "TX<5>" LOC = "T18" ;
+#NET "TX<4>" LOC = "T17" ;
+#NET "TX<3>" LOC = "W19" ;
+#NET "TX<2>" LOC = "V20" ;
+#NET "TX<1>" LOC = "Y21" ;
+#NET "TX<0>" LOC = "AA22" ;
+#NET "TXSYNC" LOC = "U18" ;
+#NET "TXBLANK" LOC = "U19" ;
+
+#NET "PPS_IN" LOC = "M17" ;
+
+#NET "io_tx<0>" LOC = "AB20" ;
+#NET "io_tx<1>" LOC = "Y17" ;
+#NET "io_tx<2>" LOC = "Y16" ;
+#NET "io_tx<3>" LOC = "U16" ;
+#NET "io_tx<4>" LOC = "V16" ;
+#NET "io_tx<5>" LOC = "AB19" ;
+#NET "io_tx<6>" LOC = "AA19" ;
+#NET "io_tx<7>" LOC = "U14" ;
+#NET "io_tx<8>" LOC = "U15" ;
+#NET "io_tx<9>" LOC = "AB17" ;
+#NET "io_tx<10>" LOC = "AB18" ;
+#NET "io_tx<11>" LOC = "Y13" ;
+#NET "io_tx<12>" LOC = "W14" ;
+#NET "io_tx<13>" LOC = "U13" ;
+#NET "io_tx<14>" LOC = "AA15" ;
+#NET "io_tx<15>" LOC = "AB14" ;
+
+#NET "io_rx<0>" LOC = "Y8" ;
+#NET "io_rx<1>" LOC = "Y9" ;
+#NET "io_rx<2>" LOC = "V7" ;
+#NET "io_rx<3>" LOC = "U8" ;
+#NET "io_rx<4>" LOC = "V10" ;
+#NET "io_rx<5>" LOC = "U9" ;
+#NET "io_rx<6>" LOC = "AB7" ;
+#NET "io_rx<7>" LOC = "AA8" ;
+#NET "io_rx<8>" LOC = "W8" ;
+#NET "io_rx<9>" LOC = "V8" ;
+#NET "io_rx<10>" LOC = "AB5" ;
+#NET "io_rx<11>" LOC = "AB6" ;
+#NET "io_rx<12>" LOC = "AB4" ;
+#NET "io_rx<13>" LOC = "AA4" ;
+#NET "io_rx<14>" LOC = "W5" ;
+#NET "io_rx<15>" LOC = "Y4" ;
+
+#NET "CLKOUT2_CODEC" LOC = "U12" ;
+#NET "CLKOUT1_CODEC" LOC = "V12" ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "AB21" ;
+#NET "fpga_cfg_din" LOC = "W17" ;
+#NET "fpga_cfg_cclk" LOC = "V17" ;
+#NET "fpga_cfg_init_b" LOC = "W15" ;
+
+## Unnamed, need to figure out what they do
+#NET "unnamed_net37" LOC = "B1" ;
+#NET "unnamed_net36" LOC = "B22" ;
+#NET "unnamed_net35" LOC = "D2" ;
+#NET "unnamed_net34" LOC = "A21" ;
+#NET "unnamed_net45" LOC = "F7" ;
+#NET "unnamed_net44" LOC = "V6" ;
+#NET "unnamed_net43" LOC = "AA3" ;
+#NET "unnamed_net42" LOC = "AB3" ;
+
+#NET "GND" LOC = "V19" ;
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
new file mode 100644
index 000000000..e28a6a582
--- /dev/null
+++ b/usrp2/top/u1e/u1e.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e
+ (
+ input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+
+ // GPMC
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A,
+ input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE
+ );
+
+ // FPGA-specific pins connections
+ wire clk_fpga;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
+ clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+ // Debug circuitry
+ reg [31:0] ctr;
+ always @(posedge clk_fpga)
+ ctr <= ctr + 1;
+
+
+ assign debug_led = ctr[27:25];
+ assign debug_clk = { EM_CLK, clk_fpga };
+ assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ { EM_D } };
+
+ wire EM_output_enable = (~EM_NOE & ~EM_NCS4);
+ wire [15:0] EM_D_out;
+
+ assign EM_D = EM_output_enable ? EM_D_out : 16'bz;
+
+ ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
+ (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out),
+ .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
+
+
+endmodule // u2plus
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