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-rw-r--r--usrp2/top/Makefile.common51
-rw-r--r--usrp2/top/tcl/ise_helper.tcl17
-rw-r--r--usrp2/top/u2_rev3/Makefile240
-rw-r--r--usrp2/top/u2_rev3/Makefile.udp240
-rw-r--r--[-rwxr-xr-x]usrp2/top/u2_rev3/u2_core.v3
5 files changed, 130 insertions, 421 deletions
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
new file mode 100644
index 000000000..02b1b9529
--- /dev/null
+++ b/usrp2/top/Makefile.common
@@ -0,0 +1,51 @@
+#
+# Copyright 2008, 2009, 2010 Ettus Research LLC
+#
+
+##################################################
+# Constants
+##################################################
+BASE_DIR = $(abspath ..)
+ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).ise
+BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
+MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
+
+##################################################
+# Global Targets
+##################################################
+all: bin
+
+proj: $(ISE_FILE)
+
+check: $(ISE_FILE)
+ $(ISE_HELPER) "Check Syntax"
+
+synth: $(ISE_FILE)
+ $(ISE_HELPER) "Synthesize - XST"
+
+bin: $(BIN_FILE)
+
+mcs: $(MCS_FILE)
+
+clean:
+ $(RM) -r $(BUILD_DIR)
+
+.PHONY: all proj check synth bin mcs clean
+
+##################################################
+# Dependency Targets
+##################################################
+$(ISE_FILE): $(SOURCES)
+ @echo $@
+ $(ISE_HELPER) ""
+
+$(BIN_FILE): $(ISE_FILE)
+ @echo $@
+ $(ISE_HELPER) "Generate Programming File"
+ touch $@
+
+$(MCS_FILE): $(BIN_FILE)
+ promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE)
+
+.EXPORT_ALL_VARIABLES:
diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl
index fe9db87af..a4bee76b8 100644
--- a/usrp2/top/tcl/ise_helper.tcl
+++ b/usrp2/top/tcl/ise_helper.tcl
@@ -40,12 +40,12 @@ proc set_props {process options} {
}
}
-if [file isfile $env(PROJ_FILE)] {
- puts ">>> Opening project: $env(PROJ_FILE)"
- project open $env(PROJ_FILE)
+if [file isfile $env(ISE_FILE)] {
+ puts ">>> Opening project: $env(ISE_FILE)"
+ project open $env(ISE_FILE)
} else {
- puts ">>> Creating project: $env(PROJ_FILE)"
- project new $env(PROJ_FILE)
+ puts ">>> Creating project: $env(ISE_FILE)"
+ project new $env(ISE_FILE)
##################################################
# Set the project properties
@@ -56,7 +56,6 @@ if [file isfile $env(PROJ_FILE)] {
# Add the sources
##################################################
foreach source $env(SOURCES) {
- set source $env(SOURCE_ROOT)$source
puts ">>> Adding source to project: $source"
xfile add $source
}
@@ -78,9 +77,9 @@ if [file isfile $env(PROJ_FILE)] {
set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
}
-if [string compare $env(PROCESS_RUN) ""] {
- puts ">>> Running Process: $env(PROCESS_RUN)"
- process run $env(PROCESS_RUN)
+if [string compare [lindex $argv 0] ""] {
+ puts ">>> Running Process: [lindex $argv 0]"
+ process run [lindex $argv 0]
}
project close
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 3a8edc9ac..68c296b9b 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -1,42 +1,34 @@
#
# Copyright 2008 Ettus Research LLC
-#
-# This file is part of GNU Radio
-#
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING. If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-#
+#
##################################################
-# xtclsh Shell and tcl Script Path
+# Project Setup
##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build$(ISE))
##################################################
-# Project Setup
+# Include other makefiles
##################################################
-BUILD_DIR := build$(ISE)/
-export TOP_MODULE := u2_rev3
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
##################################################
# Project Properties
##################################################
-export PROJECT_PROPERTIES := \
+PROJECT_PROPERTIES = \
family Spartan3 \
device xc3s2000 \
package fg456 \
@@ -51,159 +43,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \
##################################################
# Sources
##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio.v \
-control_lib/ram_2port.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus.v \
-control_lib/settings_bus_crossclock.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-control_lib/priority_enc.v \
-control_lib/pic.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-udp/udp_wrapper.v \
-udp/fifo19_rxrealign.v \
-udp/prot_eng_tx.v \
-udp/add_onescomp.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac_wrapper19.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo19_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo19.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-coregen/fifo_xlnx_16x19_2clk.v \
-coregen/fifo_xlnx_16x19_2clk.xco \
-coregen/fifo_xlnx_16x40_2clk.v \
-coregen/fifo_xlnx_16x40_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top.v \
-opencores/spi/rtl/verilog/timescale.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_64bit.v \
-timing/time_compare.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/simple_timer.v \
-top/u2_rev3/u2_core.v \
-top/u2_rev3/u2_rev3.ucf \
-top/u2_rev3/u2_rev3.v
+TOP_SRCS = \
+u2_core.v \
+u2_rev3.v \
+u2_rev3.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
##################################################
# Process Properties
##################################################
-export SYNTHESIZE_PROPERTIES := \
+SYNTHESIZE_PROPERTIES = \
"Number of Clock Buffers" 8 \
"Pack I/O Registers into IOBs" Yes \
"Optimization Effort" High \
@@ -213,10 +66,10 @@ export SYNTHESIZE_PROPERTIES := \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
@@ -227,41 +80,18 @@ export MAP_PROPERTIES := \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \
"Report Type" "Error Report"
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
"Configuration Rate" 6 \
"Create Binary Configuration File" TRUE \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" TRUE \
"Enable Outputs (Output Events)" 6
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
- @echo make proj, check, synth, bin, or clean
-
-proj:
- PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
-
-check:
- PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
-
-synth:
- PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
-
-bin:
- PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
-
-clean:
- rm -rf $(BUILD_DIR)
-
-
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
index f6e6e5b15..9962887d4 100644
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ b/usrp2/top/u2_rev3/Makefile.udp
@@ -1,42 +1,34 @@
#
# Copyright 2008 Ettus Research LLC
-#
-# This file is part of GNU Radio
-#
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING. If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-#
+#
##################################################
-# xtclsh Shell and tcl Script Path
+# Project Setup
##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build-udp$(ISE))
##################################################
-# Project Setup
+# Include other makefiles
##################################################
-BUILD_DIR := build-udp$(ISE)/
-export TOP_MODULE := u2_rev3
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
##################################################
# Project Properties
##################################################
-export PROJECT_PROPERTIES := \
+PROJECT_PROPERTIES = \
family Spartan3 \
device xc3s2000 \
package fg456 \
@@ -51,159 +43,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \
##################################################
# Sources
##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio.v \
-control_lib/ram_2port.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus.v \
-control_lib/settings_bus_crossclock.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-control_lib/priority_enc.v \
-control_lib/pic.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-udp/udp_wrapper.v \
-udp/fifo19_rxrealign.v \
-udp/prot_eng_tx.v \
-udp/add_onescomp.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac_wrapper19.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo19_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo19.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-coregen/fifo_xlnx_16x19_2clk.v \
-coregen/fifo_xlnx_16x19_2clk.xco \
-coregen/fifo_xlnx_16x40_2clk.v \
-coregen/fifo_xlnx_16x40_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top.v \
-opencores/spi/rtl/verilog/timescale.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx_udp.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_64bit.v \
-timing/time_compare.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/simple_timer.v \
-top/u2_rev3/u2_core_udp.v \
-top/u2_rev3/u2_rev3.ucf \
-top/u2_rev3/u2_rev3.v
+TOP_SRCS = \
+u2_core_udp.v \
+u2_rev3.v \
+u2_rev3.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
##################################################
# Process Properties
##################################################
-export SYNTHESIZE_PROPERTIES := \
+SYNTHESIZE_PROPERTIES = \
"Number of Clock Buffers" 8 \
"Pack I/O Registers into IOBs" Yes \
"Optimization Effort" High \
@@ -213,10 +66,10 @@ export SYNTHESIZE_PROPERTIES := \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
@@ -227,41 +80,18 @@ export MAP_PROPERTIES := \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \
"Report Type" "Error Report"
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
"Configuration Rate" 6 \
"Create Binary Configuration File" TRUE \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" TRUE \
"Enable Outputs (Output Events)" 6
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
- @echo make proj, check, synth, bin, or clean
-
-proj:
- PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
-
-check:
- PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
-
-synth:
- PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
-
-bin:
- PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
-
-clean:
- rm -rf $(BUILD_DIR)
-
-
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index c2e1bab63..b67d8edd6 100755..100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -582,8 +582,7 @@ module u2_core
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
.debug_rx(debug_rx) );
- // dummy_rx dsp_core_rx
- dsp_core_rx dsp_core_rx
+ dsp_core_rx_old dsp_core_rx_old
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 01:43:08 +0000