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-rw-r--r--usrp2/top/B100/Makefile.B10015
-rw-r--r--usrp2/top/B100/u1plus_core.v4
-rw-r--r--usrp2/top/E1x0/Makefile.E10010
-rw-r--r--usrp2/top/E1x0/Makefile.E11010
-rw-r--r--usrp2/top/E1x0/u1e_core.v2
-rw-r--r--usrp2/top/N2x0/Makefile.N200R310
-rw-r--r--usrp2/top/N2x0/Makefile.N200R49
-rw-r--r--usrp2/top/N2x0/Makefile.N210R310
-rw-r--r--usrp2/top/N2x0/Makefile.N210R49
-rw-r--r--usrp2/top/USRP2/Makefile10
10 files changed, 61 insertions, 28 deletions
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 442b0b579..3cdbb62c0 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -7,7 +7,14 @@
##################################################
TOP_MODULE := B100
BUILD_DIR := build-B100/
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
include ../Makefile.common
include ../../fifo/Makefile.srcs
@@ -21,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpif/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -64,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 4c3acaa27..88a8b4f4b 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -37,7 +37,7 @@ module u1plus_core
input pps_in
);
- localparam TXFIFOSIZE = 12;
+ localparam TXFIFOSIZE = 11;
localparam RXFIFOSIZE = 12;
// 64 total regs in address space
@@ -220,7 +220,7 @@ module u1plus_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(0/*no engine*/),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 397bac618..ad5a0c1bd 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u1e
BUILD_DIR = $(abspath build$(ISE)-E100)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpmc/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 1f95954ae..291ac0a44 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u1e
BUILD_DIR = $(abspath build$(ISE)-E110)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpmc/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 5f2edca1a..765023e29 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -220,7 +220,7 @@ module u1e_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3
index 7181e7d62..680cadf44 100644
--- a/usrp2/top/N2x0/Makefile.N200R3
+++ b/usrp2/top/N2x0/Makefile.N200R3
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2plus
BUILD_DIR = $(abspath build$(ISE)-N200R3)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4
index 551f7a232..5c9ffd7a6 100644
--- a/usrp2/top/N2x0/Makefile.N200R4
+++ b/usrp2/top/N2x0/Makefile.N200R4
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2plus
BUILD_DIR = $(abspath build$(ISE)-N200R4)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
@@ -69,7 +72,7 @@ SYNTHESIZE_PROPERTIES = \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
-"Verilog Macros" "LVDS=1"
+"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3
index 2514600f4..0b53ac951 100644
--- a/usrp2/top/N2x0/Makefile.N210R3
+++ b/usrp2/top/N2x0/Makefile.N210R3
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2plus
BUILD_DIR = $(abspath build$(ISE)-N210R3)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4
index 951df0c7c..a7d2a9b49 100644
--- a/usrp2/top/N2x0/Makefile.N210R4
+++ b/usrp2/top/N2x0/Makefile.N210R4
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2plus
BUILD_DIR = $(abspath build$(ISE)-N210R4)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
@@ -69,7 +72,7 @@ SYNTHESIZE_PROPERTIES = \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
-"Verilog Macros" "LVDS=1"
+"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile
index adfaf06c4..1fc375c76 100644
--- a/usrp2/top/USRP2/Makefile
+++ b/usrp2/top/USRP2/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2_rev3
BUILD_DIR = $(abspath build)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 19:37:04 +0000