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-rw-r--r--usrp2/top/B100/Makefile.B1003
-rwxr-xr-xusrp2/top/B100/core_compile2
-rw-r--r--usrp2/top/B100/u1plus_core.v59
-rw-r--r--usrp2/top/E1x0/Makefile.E1003
-rw-r--r--usrp2/top/E1x0/Makefile.E1103
-rwxr-xr-xusrp2/top/E1x0/core_compile2
-rw-r--r--usrp2/top/E1x0/u1e_core.v57
-rw-r--r--usrp2/top/N2x0/Makefile.N200R34
-rw-r--r--usrp2/top/N2x0/Makefile.N200R44
-rw-r--r--usrp2/top/N2x0/Makefile.N210R34
-rw-r--r--usrp2/top/N2x0/Makefile.N210R44
-rw-r--r--usrp2/top/N2x0/u2plus_core.v83
-rw-r--r--usrp2/top/USRP2/Makefile4
-rw-r--r--usrp2/top/USRP2/u2_core.v83
14 files changed, 190 insertions, 125 deletions
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 90dd25942..442b0b579 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -21,6 +21,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpif/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -50,7 +51,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPIF_SRCS)
+$(GPIF_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile
index b2ccc8b49..b62cbaee0 100755
--- a/usrp2/top/B100/core_compile
+++ b/usrp2/top/B100/core_compile
@@ -1 +1 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 0bada703c..1981123bc 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -56,6 +56,7 @@ module u1plus_core
localparam SR_CLEAR_RX_FIFO = 61; // 1 reg
localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
localparam SR_GLOBAL_RESET = 63; // 1 reg
+ localparam SR_USER_REGS = 64; // 2 regs
localparam SR_GPIO = 128; // 5 regs
@@ -65,11 +66,11 @@ module u1plus_core
wire pps_int;
wire [63:0] vita_time, vita_time_pps;
reg [15:0] reg_cgen_ctrl, reg_test;
-
- wire [7:0] set_addr;
- wire [31:0] set_data;
- wire set_stb;
-
+
+ wire [7:0] set_addr, set_addr_user;
+ wire [31:0] set_data, set_data_user;
+ wire set_stb, set_stb_user;
+
wire [31:0] debug0;
wire [31:0] debug1;
@@ -137,20 +138,20 @@ module u1plus_core
.tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif),
- .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl),
+ .test_len(0), .test_rate(0), .test_ctrl(0),
.debug0(debug0), .debug1(debug1));
// /////////////////////////////////////////////////////////////////////////
// RX ADC Frontend, does IQ Balance, DC Offset, muxing
- wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p
+ wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_a({rx_i,4'b00}),.adc_ovf_a(0),
.adc_b({rx_q,4'b00}),.adc_ovf_b(0),
- .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug());
+ .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug());
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
@@ -160,15 +161,16 @@ module u1plus_core
wire [35:0] vita_rx_data0;
wire vita_rx_src_rdy0, vita_rx_dst_rdy0;
- dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0
- (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx),
+ (.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(rx_overrun_dsp0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
@@ -183,15 +185,16 @@ module u1plus_core
wire [35:0] vita_rx_data1;
wire vita_rx_src_rdy1, vita_rx_dst_rdy1;
- dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1
- (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx),
+ (.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(rx_overrun_dsp1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
@@ -210,10 +213,12 @@ module u1plus_core
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
- wire [23:0] tx_i_int, tx_q_int;
wire run_tx;
-
- vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ wire [23:0] tx_fe_i, tx_fe_q;
+ wire [31:0] sample_tx;
+ wire strobe_tx;
+
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
@@ -223,14 +228,22 @@ module u1plus_core
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
- .tx_i(tx_i_int),.tx_q(tx_q_int),
+ .sample(sample_tx), .strobe(strobe_tx),
.underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
+ (.clk(wb_clk),.rst(wb_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug() );
+
tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
(.clk(wb_clk), .rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1),
+ .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
.dac_a(tx_i), .dac_b(tx_q));
// /////////////////////////////////////////////////////////////////////////////////////
@@ -392,6 +405,12 @@ module u1plus_core
.wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
.strobe(set_stb),.addr(set_addr),.data(set_data) );
+ user_settings #(.BASE(SR_USER_REGS)) user_settings
+ (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb),
+ .set_addr(set_addr),.set_data(set_data),
+ .set_addr_user(set_addr_user),.set_data_user(set_data_user),
+ .set_stb_user(set_stb_user) );
+
// /////////////////////////////////////////////////////////////////////////
// Readback mux 32 -- Slave #7
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100
index 9b9a48911..397bac618 100644
--- a/usrp2/top/E1x0/Makefile.E100
+++ b/usrp2/top/E1x0/Makefile.E100
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpmc/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -53,7 +54,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPMC_SRCS)
+$(GPMC_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index be2761baf..1f95954ae 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpmc/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -53,7 +54,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPMC_SRCS)
+$(GPMC_SRCS) $(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile
index 02d7f006e..14e138fa3 100755
--- a/usrp2/top/E1x0/core_compile
+++ b/usrp2/top/E1x0/core_compile
@@ -1,3 +1,3 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index aede63bac..d3495707d 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -59,6 +59,7 @@ module u1e_core
localparam SR_CLEAR_RX_FIFO = 61; // 1 reg
localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
localparam SR_GLOBAL_RESET = 63; // 1 reg
+ localparam SR_USER_REGS = 64; // 2 regs
localparam SR_GPIO = 128; // 5 regs
@@ -70,10 +71,10 @@ module u1e_core
reg [15:0] reg_cgen_ctrl, reg_test, xfer_rate;
wire [7:0] test_rate;
wire [3:0] test_ctrl;
-
- wire [7:0] set_addr;
- wire [31:0] set_data;
- wire set_stb;
+
+ wire [7:0] set_addr, set_addr_user;
+ wire [31:0] set_data, set_data_user;
+ wire set_stb, set_stb_user;
wire [31:0] debug_vt;
wire rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
@@ -142,7 +143,7 @@ module u1e_core
// /////////////////////////////////////////////////////////////////////////
// RX ADC Frontend, does IQ Balance, DC Offset, muxing
- wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p
+ wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p
wire run_rx0, run_rx1;
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
@@ -150,7 +151,7 @@ module u1e_core
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_a({rx_i,4'b00}),.adc_ovf_a(0),
.adc_b({rx_q,4'b00}),.adc_ovf_b(0),
- .i_out(adc_i), .q_out(adc_q), .run(run_rx0 | run_rx1), .debug());
+ .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug());
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
@@ -160,15 +161,16 @@ module u1e_core
wire [35:0] vita_rx_data0;
wire vita_rx_src_rdy0, vita_rx_dst_rdy0;
- dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0
- (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx),
+ (.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(rx_overrun_dsp0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
@@ -183,15 +185,16 @@ module u1e_core
wire [35:0] vita_rx_data1;
wire vita_rx_src_rdy1, vita_rx_dst_rdy1;
- dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(wb_clk),.rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1
- (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx),
+ (.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(rx_overrun_dsp1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
@@ -210,10 +213,12 @@ module u1e_core
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
- wire [23:0] tx_i_int, tx_q_int;
wire run_tx;
-
- vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ wire [23:0] tx_fe_i, tx_fe_q;
+ wire [31:0] sample_tx;
+ wire strobe_tx;
+
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
@@ -223,14 +228,22 @@ module u1e_core
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
- .tx_i(tx_i_int),.tx_q(tx_q_int),
+ .sample(sample_tx), .strobe(strobe_tx),
.underrun(tx_underrun_dsp), .run(run_tx),
.debug(debug_vt));
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
+ (.clk(wb_clk),.rst(wb_rst),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug() );
+
tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
(.clk(wb_clk), .rst(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1),
+ .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
.dac_a(tx_i), .dac_b(tx_q));
// /////////////////////////////////////////////////////////////////////////////////////
@@ -432,11 +445,17 @@ module u1e_core
.wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
.strobe(set_stb),.addr(set_addr),.data(set_data) );
+ user_settings #(.BASE(SR_USER_REGS)) user_settings
+ (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb),
+ .set_addr(set_addr),.set_data(set_data),
+ .set_addr_user(set_addr_user),.set_data_user(set_data_user),
+ .set_stb_user(set_stb_user) );
+
// /////////////////////////////////////////////////////////////////////////
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd1}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wire [31:0] reg_test32;
diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3
index 9ed5ece00..7181e7d62 100644
--- a/usrp2/top/N2x0/Makefile.N200R3
+++ b/usrp2/top/N2x0/Makefile.N200R3
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -52,7 +53,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4
index f8640224f..551f7a232 100644
--- a/usrp2/top/N2x0/Makefile.N200R4
+++ b/usrp2/top/N2x0/Makefile.N200R4
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -53,7 +54,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3
index 2937dc409..2514600f4 100644
--- a/usrp2/top/N2x0/Makefile.N210R3
+++ b/usrp2/top/N2x0/Makefile.N210R3
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -52,7 +53,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4
index 39a2508f9..951df0c7c 100644
--- a/usrp2/top/N2x0/Makefile.N210R4
+++ b/usrp2/top/N2x0/Makefile.N210R4
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -53,7 +54,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 3ead0db8e..f04d449be 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -152,7 +152,7 @@ module u2plus_core
localparam SR_SIMTIMER = 8; // 2
localparam SR_TIME64 = 10; // 6
localparam SR_BUF_POOL = 16; // 4
-
+ localparam SR_USER_REGS = 20; // 2
localparam SR_RX_FRONT = 24; // 5
localparam SR_RX_CTRL0 = 32; // 9
localparam SR_RX_DSP0 = 48; // 7
@@ -170,15 +170,16 @@ module u2plus_core
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
// localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
localparam DSP_RX_FIFOSIZE = 10;
+ localparam DSP_TX_FIFOSIZE = 10;
localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo?
-
- wire [7:0] set_addr, set_addr_dsp;
- wire [31:0] set_data, set_data_dsp;
- wire set_stb, set_stb_dsp;
-
+
+ wire [7:0] set_addr, set_addr_dsp, set_addr_user;
+ wire [31:0] set_data, set_data_dsp, set_data_user;
+ wire set_stb, set_stb_dsp, set_stb_user;
+
reg wb_rst;
wire dsp_rst = wb_rst;
@@ -435,7 +436,7 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd2}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -478,7 +479,13 @@ module u2plus_core
settings_bus_crossclock settings_bus_crossclock
(.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
.clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
-
+
+ user_settings #(.BASE(SR_USER_REGS)) user_settings
+ (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),
+ .set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_addr_user(set_addr_user),.set_data_user(set_data_user),
+ .set_stb_user(set_stb_user) );
+
// Output control lines
wire [7:0] clock_outs, serdes_outs, adc_outs;
assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
@@ -559,37 +566,33 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// ADC Frontend
- wire [23:0] adc_i, adc_q;
+ wire [23:0] rx_fe_i, rx_fe_q;
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
.adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
- .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+ .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
wire [31:0] sample_rx0;
- wire clear_rx0, strobe_rx0;
+ wire strobe_rx0;
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
- dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
- setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0
- (.clk(dsp_clk),.rst(dsp_rst),
- .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
- .out(),.changed(clear_rx0));
-
vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
@@ -599,25 +602,21 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// DSP RX 1
wire [31:0] sample_rx1;
- wire clear_rx1, strobe_rx1;
+ wire strobe_rx1;
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
- dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
- setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1
- (.clk(dsp_clk),.rst(dsp_rst),
- .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
- .out(),.changed(clear_rx1));
-
vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
@@ -632,10 +631,6 @@ module u2plus_core
wire [31:0] debug_vt;
wire clear_tx;
- setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx
- (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),
- .in(set_data_dsp),.out(),.changed(clear_tx));
-
assign RAM_A[20:18] = 3'b0;
ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18))
@@ -661,9 +656,12 @@ module u2plus_core
.debug(debug_extfifo),
.debug2(debug_extfifo2) );
- wire [23:0] tx_i, tx_q;
+ wire [23:0] tx_fe_i, tx_fe_q;
+ wire [31:0] sample_tx;
+ wire strobe_tx;
- vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
+ .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
.PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
.DSP_NUMBER(0))
@@ -673,16 +671,25 @@ module u2plus_core
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
- .tx_i(tx_i),.tx_q(tx_q),
+ .sample(sample_tx), .strobe(strobe_tx),
.underrun(underrun), .run(run_tx),
+ .clear_vita(clear_tx), //output internal vita clear signal
.debug(debug_vt));
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug() );
+
tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .tx_i(tx_i), .tx_q(tx_q), .run(1'b1),
+ .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
.dac_a(dac_a), .dac_b(dac_b));
-
+
// ///////////////////////////////////////////////////////////////////////////////////
// SERDES
diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile
index 8ebb43639..adfaf06c4 100644
--- a/usrp2/top/USRP2/Makefile
+++ b/usrp2/top/USRP2/Makefile
@@ -24,6 +24,7 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
+include ../../custom/Makefile.srcs
##################################################
@@ -52,7 +53,8 @@ u2_rev3.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index bbd0e9337..d29f31b8f 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -157,7 +157,7 @@ module u2_core
localparam SR_SIMTIMER = 8; // 2
localparam SR_TIME64 = 10; // 6
localparam SR_BUF_POOL = 16; // 4
-
+ localparam SR_USER_REGS = 20; // 2
localparam SR_RX_FRONT = 24; // 5
localparam SR_RX_CTRL0 = 32; // 9
localparam SR_RX_DSP0 = 48; // 7
@@ -175,15 +175,16 @@ module u2_core
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
// localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
localparam DSP_RX_FIFOSIZE = 10;
+ localparam DSP_TX_FIFOSIZE = 10;
localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo?
-
- wire [7:0] set_addr, set_addr_dsp;
- wire [31:0] set_data, set_data_dsp;
- wire set_stb, set_stb_dsp;
-
+
+ wire [7:0] set_addr, set_addr_dsp, set_addr_user;
+ wire [31:0] set_data, set_data_dsp, set_data_user;
+ wire set_stb, set_stb_dsp, set_stb_user;
+
wire ram_loader_done, ram_loader_rst;
wire wb_rst;
wire dsp_rst = wb_rst;
@@ -441,7 +442,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd2}; //major, minor
+ localparam compat_num = {16'd9, 16'd0}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -484,7 +485,13 @@ module u2_core
settings_bus_crossclock settings_bus_crossclock
(.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
.clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
-
+
+ user_settings #(.BASE(SR_USER_REGS)) user_settings
+ (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),
+ .set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_addr_user(set_addr_user),.set_data_user(set_data_user),
+ .set_stb_user(set_stb_user) );
+
// Output control lines
wire [7:0] clock_outs, serdes_outs, adc_outs;
assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
@@ -547,37 +554,33 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// ADC Frontend
- wire [23:0] adc_i, adc_q;
+ wire [23:0] rx_fe_i, rx_fe_q;
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
.adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
- .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+ .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
wire [31:0] sample_rx0;
- wire clear_rx0, strobe_rx0;
+ wire strobe_rx0;
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
- dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
- setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0
- (.clk(dsp_clk),.rst(dsp_rst),
- .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
- .out(),.changed(clear_rx0));
-
vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
@@ -587,25 +590,21 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// DSP RX 1
wire [31:0] sample_rx1;
- wire clear_rx1, strobe_rx1;
+ wire strobe_rx1;
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
- dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
- setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1
- (.clk(dsp_clk),.rst(dsp_rst),
- .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
- .out(),.changed(clear_rx1));
-
vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
- (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
@@ -620,10 +619,6 @@ module u2_core
wire [31:0] debug_vt;
wire clear_tx;
- setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx
- (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),
- .in(set_data_dsp),.out(),.changed(clear_tx));
-
ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19))
ext_fifo_i1
(.int_clk(dsp_clk),
@@ -647,9 +642,12 @@ module u2_core
.debug(debug_extfifo),
.debug2(debug_extfifo2) );
- wire [23:0] tx_i, tx_q;
+ wire [23:0] tx_fe_i, tx_fe_q;
+ wire [31:0] sample_tx;
+ wire strobe_tx;
- vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
+ .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
.PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
.DSP_NUMBER(0))
@@ -659,16 +657,25 @@ module u2_core
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
- .tx_i(tx_i),.tx_q(tx_q),
+ .sample(sample_tx), .strobe(strobe_tx),
.underrun(underrun), .run(run_tx),
+ .clear_vita(clear_tx), //output internal vita clear signal
.debug(debug_vt));
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+ .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug() );
+
tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .tx_i(tx_i), .tx_q(tx_q), .run(1'b1),
+ .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
.dac_a(dac_a), .dac_b(dac_b));
-
+
// ///////////////////////////////////////////////////////////////////////////////////
// SERDES
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-21 23:25:51 +0000