diff options
Diffstat (limited to 'usrp2/top/u2_rev3')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 2 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 15 |
2 files changed, 10 insertions, 7 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 124930c23..c9502898b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -425,7 +425,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd1; + localparam compat_num = 32'd2; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 3a43e4ffe..4daa66212 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -203,12 +203,13 @@ module u2_rev3 reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + // ADC A and B are swapped in schematic to facilitate clean layout always @(posedge dsp_clk) begin - adc_a_reg1 <= adc_a; - adc_b_reg1 <= adc_b; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_b_reg1 <= adc_ovf_b; + adc_a_reg1 <= adc_b; + adc_b_reg1 <= adc_a; + adc_ovf_a_reg1 <= adc_ovf_b; + adc_ovf_b_reg1 <= adc_ovf_a; end always @(posedge dsp_clk) @@ -327,8 +328,10 @@ module u2_rev3 end wire [15:0] dac_a_int, dac_b_int; - always @(negedge dsp_clk) dac_a <= dac_a_int; - always @(negedge dsp_clk) dac_b <= dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) dac_a <= ~dac_b_int; + always @(negedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst |